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公开(公告)号：KR101512844B1
公开(公告)日：2015-04-21
申请号：KR1020080010651
申请日：2008-02-01
Applicant: 삼성전자주식회사
Abstract: 본 발명은 불소계 고분자를 포함하거나 퍼플루오로폴리이써(Perfluoropolyether:PFPE) 유도체와 PFPE-혼화성 고분자를 포함하는 항산화막용 조성물, 이를 이용한 항산화막 형성방법 및 이로부터 제조된 전자부품용 기재에 관한 것이다. 본 발명의 조성물을 이용하면 용액 공정에 의해 항산화막을 형성할 수 있고, 전도성이 우수하고 제조 단가가 낮은 금속을 사용한 전자부품용 기재를 제공할 수 있다.
불소계 고분자, 항산화막, 퍼플루오로폴리이써, 광경화제, 전자부품용 기재Abstract translation: 涉及：（PFPE全氟聚醚）衍生物和抗氧化剂的PFPE-膜组合物，包含可混溶的聚合物，抗氧化膜的形成方法及用于从中与此制备电子部件的基体材料，本发明包括一种氟化聚合物，或写聚酰亚胺的全氟烷 。 与本发明的组合物可以形成通过溶液方法的抗氧化剂的膜，导电性可以是优秀的，制造成本是对于具有低金属电子元件提供衬底。
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公开(公告)号：KR101194842B1
公开(公告)日：2012-10-25
申请号：KR1020070090563
申请日：2007-09-06
Applicant: 삼성전자주식회사
CPC classification number: H01L23/13 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2224/83 , H01L2225/0651 , H01L2225/06524 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01087 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/185 , H05K2201/09509 , H05K2201/10515 , H05K2201/10719 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
Abstract: 반도체 패키지가 삽입된 인쇄회로기판에 관해 개시한다. 이를 위해 본 발명은 반도체 패키지를 끼워 넣을 수 있는 홈부(groove portion)가 형성된 인쇄회로기판 베이스와, 상기 인쇄회로기판 베이스의 홈부에 삽입되고 엔캡슐레이션(encapsulation)이 완료된 형태의 반도체 패키지와, 상기 반도체 패키지가 삽입된 인쇄회로기판 베이스의 상부면을 덮는 빌드 업 레진(build up resin) 패턴과, 상기 빌드 업 레진 패턴 상부에 형성되고 상기 반도체 패키지의 연결단자를 외부로 연장시키는 인쇄회로패턴과, 상기 인쇄회로패턴이 형성된 상기 인쇄회로기판 베이스를 덮는 솔더 레지스트를 구비하는 것을 특징으로 하는 반도체 패키지가 삽입된 인쇄회로기판을 제공한다. 따라서 검증이 완료된 반도체 소자를 인쇄회로기판에 삽입함으로써 불량률을 떨어뜨리고 반도체 패키지의 신뢰성에 대한 향상시킬 수 있다.
반도체 패키지, 인쇄회로기판, 신뢰도, 전기적 검사, 미세 피치.-
公开(公告)号：KR1020090044636A
公开(公告)日：2009-05-07
申请号：KR1020070110814
申请日：2007-11-01
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/315 , H01L23/562 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/13022 , H01L2224/73253 , H01L2924/00014 , H01L2924/14 , H01L2924/15331 , H01L2924/1815 , H01L2224/05599
Abstract: 본 발명은 반도체 칩 패키지를 제공한다. 본 발명의 실시예들에 따른 상기 반도체 패키지는 반도체 소자가 형성된 반도체 칩의 6면 모두를 하나의 몰딩막으로 덮인다. 상기 몰딩막은 상기 반도체 칩의 배면을 노출하는 적어도 하나의 오프닝을 갖는다.
반도체, 패키지, 몰딩막, 보호-
公开(公告)号：KR1020090025593A
公开(公告)日：2009-03-11
申请号：KR1020070090563
申请日：2007-09-06
Applicant: 삼성전자주식회사
CPC classification number: H01L23/13 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2224/83 , H01L2225/0651 , H01L2225/06524 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01087 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/185 , H05K2201/09509 , H05K2201/10515 , H05K2201/10719 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
Abstract: A semiconductor package embedded printed circuit board is provided to improve the reliability of the semiconductor package by using the semiconductor package to complete verification. A groove portion(102) is formed in a printed circuit board base(100). A semiconductor package(120) is inserted into the groove portion of the printed circuit board base and the encapsulation is completed in the semiconductor package. A build up resin pattern(110) covers an upper side of the printed circuit board base. A printed circuit board(130) is formed in the upper side of the build up resin pattern and extends an interconnection terminal(104) to the external. A solder resist(140) covers the printed circuit board base with the printed circuit board.
Abstract translation: 提供半导体封装的嵌入式印刷电路板，以通过使用半导体封装来完成验证来提高半导体封装的可靠性。 在印刷电路基板（100）上形成有槽部（102）。 将半导体封装（120）插入到印刷电路板基底的凹槽部分中，并且在半导体封装中完成封装。 积层树脂图案（110）覆盖印刷电路板基底的上侧。 印刷电路板（130）形成在构成树脂图案的上侧，并将互连端子（104）延伸到外部。 阻焊剂（140）用印刷电路板覆盖印刷电路板底座。
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公开(公告)号：KR1020080111328A
公开(公告)日：2008-12-23
申请号：KR1020070059595
申请日：2007-06-18
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L2224/73104
Abstract: A semiconductor package including a semiconductor chip package is provided to improve the electric reliability of a semiconductor chip package by including a molding layer having a meniscus concave. A semiconductor chip package comprises a semiconductor chip(110), a solder ball(112) for a bump and a molding layer(120). The semiconductor chip includes a side including bonding pads, a second side facing the first side and a side. The solder ball for a bump is provided on bonding pads. The molding layer is provided so that each part of the solder balls for bump is exposed with covering the first side. The molding layer between the adjacent solder balls for bumps has a meniscus concave. The solder balls for bump comprise a cross section having a maximum diameter parallel to the first side. Height from the first side to the edge contacting with the solder ball for the bump of the meniscus concave is within 1/7 length of the maximum diameter of the solder ball to a lower part or upper part.
Abstract translation: 提供了包括半导体芯片封装的半导体封装，以通过包括具有弯月面凹陷的模制层来改善半导体芯片封装的电可靠性。 半导体芯片封装包括半导体芯片（110），用于凸块的焊球（112）和模制层（120）。 半导体芯片包括包括接合焊盘的一侧，面向第一侧和第二侧的第二侧。 用于凸块的焊球设置在焊盘上。 提供成型层，使得用于凸起的焊球的每一部分都被覆盖在第一面上。 用于凸起的相邻焊球之间的模制层具有弯月面凹陷。 用于凸块的焊球包括具有与第一侧平行的最大直径的横截面。 与焊球接触的第一侧到边缘的高度，用于弯月面凹陷的凸起的距离在焊球的最大直径与下部或上部的1/7长度内。
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Patent Agency Ranking
公开(公告)号：KR1020080111211A
公开(公告)日：2008-12-23
申请号：KR1020070059286
申请日：2007-06-18
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: H01L24/96 , H01L25/074 , H01L23/28 , H01L24/10 , H01L24/26
Abstract: A semiconductor stacked package and a method of manufacture thereof are provided to reduce the thickness of a semiconductor chip as a mold is molded on the top of the semiconductor chip. A semiconductor stacked package(80a) comprises a laminated semiconductor chip(100), a mold(120), a conductive element(110) and an outer connector. The mold is molded in the surfaces of the semiconductor chips. The conductive element electrically interconnects the semiconductor chips. The outer connector is electrically connected to an outermost semiconductor chip among the semiconductor chips. The outer connector is a solder ball or a metal bump.
Abstract translation: 提供一种半导体堆叠封装及其制造方法，以在半导体芯片的顶部上模制模具时减小半导体芯片的厚度。 半导体堆叠封装（80a）包括层叠半导体芯片（100），模具（120），导电元件（110）和外部连接器。 模具被模制在半导体芯片的表面中。 导电元件电连接半导体芯片。 外部连接器电连接到半导体芯片中的最外半导体芯片。 外部连接器是焊球或金属凸块。
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公开(公告)号：KR100846096B1
公开(公告)日：2008-07-14
申请号：KR1020070042038
申请日：2007-04-30
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L24/85 , H01L23/3121 , H01L23/562 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/83 , H01L25/0657 , H01L2224/27013 , H01L2224/29007 , H01L2224/32145 , H01L2224/32225 , H01L2224/32506 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/78301 , H01L2224/83051 , H01L2224/83101 , H01L2224/83194 , H01L2224/83801 , H01L2224/85181 , H01L2224/92247 , H01L2225/0651 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
Abstract: A multi-chip package and a manufacturing method thereof are provided to reduce a bouncing effect of a protruded overhang region of a semiconductor chip in a wire bonding process. A semiconductor chip(120) is disposed on a substrate(110), and then a second semiconductor chip(130) in such a way that one end of the semiconductor chip protrudes from the first semiconductor chip. An epoxy resin is applied on an overhang region of the semiconductor chip. The epoxy resin is cured to form a reinforcing member(140) for reinforcing the protruded second semiconductor chip. The first and second semiconductor chips are electrically connected to the substrate, respectively. A molding member(160) is formed on the substrate to protect the first and second semiconductor chips from external shock.
Abstract translation: 提供一种多芯片封装及其制造方法，以减少引线接合工序中的半导体芯片的突出突出部的弹跳效果。 将半导体芯片（120）设置在基板（110）上，然后以使半导体芯片的一端从第一半导体芯片突出的方式设置在第二半导体芯片（130）上。 在半导体芯片的突出部位上涂布环氧树脂。 环氧树脂被固化以形成用于加强突出的第二半导体芯片的加强构件（140）。 第一和第二半导体芯片分别电连接到基板。 模制构件（160）形成在基板上以保护第一和第二半导体芯片免受外部冲击。
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公开(公告)号：KR100817076B1
公开(公告)日：2008-03-26
申请号：KR1020060118555
申请日：2006-11-28
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/48 , H01L24/45 , H01L24/73 , H01L24/78 , H01L24/85 , H01L2224/05554 , H01L2224/32225 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45565 , H01L2224/45686 , H01L2224/4569 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/92 , H01L2224/92247 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/01049 , H01L2224/85399 , H01L2224/05599
Abstract: A partially insulation-coated metal wire for wire bonding is provided to improve adhesion with a pad while maintaining an insulation characteristic by including a partially coated insulation layer for reducing a contact area with a pad to be bonded. A partially coated insulation layer(52) is formed on the surface of a metal wire(50) in a manner that a contact area of the surface of the metal wire and a bonded pad is reduced. The metal wire has a flat section, and a part of the surface of the metal wire bonded to a pad is not coated to improve adhesion with the pad while maintaining an insulation characteristic. The lower section of the surface of the metal wire bonded to the pads is not coated.
Abstract translation: 提供用于引线接合的部分绝缘涂覆的金属线，以通过包括用于减少与要接合的焊盘的接触面积的部分涂覆的绝缘层来保持绝缘特性来改善与焊盘的粘合性。 在金属线（50）的表面上以金属线表面和接合衬垫的接触面积减小的方式形成部分被覆绝缘层（52）。 该金属线具有平坦的部分，并且在保持绝缘特性的同时，不涂覆粘合到焊盘的金属线的表面的一部分，以提高与焊盘的粘合性。 接合到焊盘的金属线的表面的下部不被涂覆。
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公开(公告)号：KR1020090084448A
公开(公告)日：2009-08-05
申请号：KR1020080010651
申请日：2008-02-01
Applicant: 삼성전자주식회사
CPC classification number: G03F7/0046 , C08G65/007 , C08G65/3353 , C08G65/336 , C08G2650/48 , C08L29/06 , C08L71/02 , H05K3/282 , H05K2201/015 , Y10T428/31529 , C08L2666/04
Abstract: A composition for forming an antioxidant film is provided to form an antioxidant film by a solution process, to be suitable for subsequent processes like Au wiring, and to ensure excellent conductivity. A composition for forming an antioxidant film comprises a fluorinated polymer; or a perfluoropolyether(PFPE) derivative of formula 1: A-CF2O(CF2CF2O)m(CF2O)nCF2-A or formula 2: CF3O(CF2CF2O)m(CF2O)nCF2-A and a PFPE-compatible polymer. In chemical formula 1 and 2, A is A' or RA' wherein A' is a functional group selected from the group consisting of COF, SiX1X2X3, silanol, chlorosilane, carboxylic acid, alcohol, amine, phosphoric acid and their derivatives, and R is C1-C30 substituted or unsubstituted alkylene group; m is 1-50: and n is 1-50.
Abstract translation: 提供了用于形成抗氧化膜的组合物，以通过溶液法形成抗氧化膜，适用于如Au布线等后续工序，并确保优异的导电性。 用于形成抗氧化膜的组合物包括含氟聚合物; 或式1的全氟聚醚（PFPE）衍生物：A-CF2O（CF2CF2O）m（CF2O）nCF2-A或式2：CF3O（CF2CF2O）m（CF2O）nCF2-A和PFPE相容的聚合物。 在化学式1和2中，A是A'或RA'，其中A'是选自COF，SiX 1 X 2 X 3，硅烷醇，氯硅烷，羧酸，醇，胺，磷酸及其衍生物的官能团，R 是C 1 -C 30取代或未取代的亚烷基; m为1-50：n为1-50。
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公开(公告)号：KR100876083B1
公开(公告)日：2008-12-26
申请号：KR1020070059595
申请日：2007-06-18
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L2224/73104
Abstract: A semiconductor package including a semiconductor chip package is provided to improve the electric reliability of a semiconductor chip package by including a molding layer having a meniscus concave. A semiconductor chip package comprises a semiconductor chip(110), a solder ball(112) for a bump and a molding layer(120). The semiconductor chip includes a side including bonding pads, a second side facing the first side and a side. The solder ball for a bump is provided on bonding pads. The molding layer is provided so that each part of the solder balls for bump is exposed with covering the first side. The molding layer between the adjacent solder balls for bumps has a meniscus concave. The solder balls for bump comprise a cross section having a maximum diameter parallel to the first side. Height from the first side to the edge contacting with the solder ball for the bump of the meniscus concave is within 1/7 length of the maximum diameter of the solder ball to a lower part or upper part.
Abstract translation: 提供包括半导体芯片封装的半导体封装，以通过包括具有弯月面凹入的模制层来提高半导体芯片封装的电可靠性。 半导体芯片封装包括半导体芯片（110），用于凸块的焊球（112）和模制层（120）。 半导体芯片包括具有接合焊盘的一侧，面对第一侧和第二侧的第二侧。 在焊盘上提供用于凸块的焊球。 提供模制层，使得用于凸块的焊球的每个部分以覆盖第一侧的方式暴露。 用于凸块的相邻焊球之间的模制层具有弯月形凹面。 用于凸块的焊球包括具有平行于第一侧的最大直径的横截面。 从弯月形凹坑的凸块接触焊球的第一侧到边缘的高度在焊球的最大直径到下半部或上半部分的长度的1/7以内。
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