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公开(公告)号：KR1020170134928A
公开(公告)日：2017-12-07
申请号：KR1020160065887
申请日：2016-05-27
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/3205 , H01L21/02 , H01L21/324
CPC classification number: H01L27/10888 , H01L21/76805 , H01L21/76883 , H01L21/76895 , H01L27/10811 , H01L27/10855 , H01L27/10885
Abstract: 본발명의실시예에따른반도체장치의제조방법은기판상에층간절연구조체를형성하는것, 상기층간절연구조체를관통하여상기기판을노출시키는콘택홀을형성하는것, 상기기판의상부면을덮는제 1 부분및 상기콘택홀의측벽들을덮는제 2 부분들을포함하는비정질실리콘막을형성하는것, 상기비정질실리콘막에수소원자들을공급하여, 상기비정질실리콘막의실리콘원자들사이의결합력을약화시키는것 및상기기판을씨드로사용하여, 상기제 1 부분을결정화시키는것을포함할수 있다.
Abstract translation: 根据本发明实施例的制造半导体器件的方法包括：在衬底上形成层间绝缘结构;形成穿过层间绝缘结构的接触孔以暴露衬底; 以及覆盖接触孔的侧壁的第二部分;向非晶硅膜提供氢原子以减弱非晶硅膜的硅原子之间的结合力; 并结晶第一部分。
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公开(公告)号：KR101486984B1
公开(公告)日：2015-01-30
申请号：KR1020080107236
申请日：2008-10-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/1052 , G11C13/0004 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
Abstract: 가변 저항 메모리 소자 및 그 형성방법이 제공된다. 상기 가변 저항 메모리 소자의 형성방법은 반도체 기판 상에 제 1 층간절연막을 형성하고, 제 1 층간절연막내에 제 1 방향으로 연장된 장방형의 상부면을 가지는 하부전극을 형성하고, 하부전극 상에 제 1 방향과 교차하는 제 2 방향으로 연장되는 장방형의 하부면을 가지며 하부전극과 접촉하는 가변저항패턴을 형성하는 것을 포함하되, 하부전극과 가변저항패턴이 접촉하는 면적은 하부전극의 상부면의 단축길이와 가변저항패턴의 하부면의 단축길이의 곱으로 표현된다.
가변저항패턴, 하부전극, 계면 저항-
公开(公告)号：KR101475741B1
公开(公告)日：2014-12-23
申请号：KR1020130048530
申请日：2013-04-30
Applicant: 삼성전자주식회사
Abstract: 오디오장치가개시된다. 오디오장치는입력되는오디오신호의포락선을검출하는포락선검출부, 선형전원과스위칭모드전원을포함하는전원공급부, 입력된오디오신호를증폭하는증폭부, 검출된포락선의전압레벨과기 설정된레벨을비교하여선형전원또는스위칭모드전원중 하나를선택하여증폭부에공급하도록전원공급부를제어하는제어부및 증폭부에서증폭된오디오신호를출력하는출력부를포함한다. 따라서, 오디오장치는최적의음질및 높은효율을구현할수 있다.
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公开(公告)号：KR1020130045702A
公开(公告)日：2013-05-06
申请号：KR1020110110082
申请日：2011-10-26
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/06 , H01L27/2409 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: PURPOSE: A method for manufacturing a non-volatile memory device is provided to reduce failure by forming a phase change material layer with uniform thickness on the whole substrate. CONSTITUTION: An interlayer insulating layer is formed on a substrate(110) having an active pattern. The interlayer insulating layer is etched to form a line pattern in the interlayer insulating layer. A sacrificial layer pattern is formed in order to fill the line pattern. The sacrificial layer pattern is etched to form a first hole(151) defined by the etched sacrificial layer pattern and the interlayer insulating layer. The etched sacrificial layer pattern is removed to form a second hole. A semiconductor layer is grown in the second hole using an SEG(Selective Epitaxial Growth) method.
Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，通过在整个衬底上形成具有均匀厚度的相变材料层来减少故障。 构成：在具有活性图案的基板（110）上形成层间绝缘层。 蚀刻层间绝缘层以在层间绝缘层中形成线图案。 形成牺牲层图案以填充线图案。 蚀刻牺牲层图案以形成由蚀刻的牺牲层图案和层间绝缘层限定的第一孔（151）。 蚀刻的牺牲层图案被去除以形成第二孔。 使用SEG（选择性外延生长）法在第二孔中生长半导体层。
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公开(公告)号：KR1020120052612A
公开(公告)日：2012-05-24
申请号：KR1020100113855
申请日：2010-11-16
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , H01L27/224 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146 , H01L29/45
Abstract: PURPOSE: A semiconductor device which includes a buffer electrode, a manufacturing method thereof, a semiconductor module including the same, and an electronic system are provided to arrange a Ti/TiN buffer electrode pattern between an ohmic contact layer and a lower electrode pattern, thereby reducing contact resistance between the lower electrode pattern and the ohmic contact layer. CONSTITUTION: A switching device(40) is formed on a substrate(110). A buffer electrode pattern(150) is formed on the switching device. A lower electrode pattern(160) is formed on a first region. A trim insulation pattern(164) is formed on a second region. A variable resistance pattern(170) is formed on the lower electrode pattern.
Abstract translation: 目的：提供包括缓冲电极的半导体器件，其制造方法，包括该缓冲电极的半导体模块和电子系统，以在欧姆接触层和下电极图案之间布置Ti / TiN缓冲电极图案，从而 降低下电极图案和欧姆接触层之间的接触电阻。 构成：开关装置（40）形成在基板（110）上。 缓冲电极图案（150）形成在开关装置上。 在第一区域上形成下电极图案（160）。 在第二区域上形成装饰绝缘图案（164）。 在下电极图案上形成可变电阻图案（170）。
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Patent Agency Ranking
公开(公告)号：KR1020100099581A
公开(公告)日：2010-09-13
申请号：KR1020090018138
申请日：2009-03-03
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L21/205
CPC classification number: H01L45/1233 , C23C16/305 , C23C16/45531 , G11C13/0004 , H01L45/06 , H01L45/144 , H01L45/1616 , H01L45/1683
Abstract: PURPOSE: A method for forming a phase-change-material film is provided to fill a contact hole without a void by forming a conformal phase-change-material film on the sidewall of the contact hole. CONSTITUTION: A first interlayer insulating film(110) is formed on a semiconductor substrate(101). A lower electrode(112) is formed on the first interlayer insulating film. An insulating film(120) is formed on the lower electrode. An opening(122), which exposes a part of the lower electrode, is formed on the insulating film. A spacer(124) is formed on the sidewall of the opening. A phase-change-material film(130) is formed to fill the opening.
Abstract translation: 目的：提供形成相变材料膜的方法，通过在接触孔的侧壁上形成保形相变材料膜来填充没有空隙的接触孔。 构成：在半导体衬底（101）上形成第一层间绝缘膜（110）。 在第一层间绝缘膜上形成下电极（112）。 在下电极上形成绝缘膜（120）。 在绝缘膜上形成露出下部电极的一部分的开口（122）。 间隔件（124）形成在开口的侧壁上。 形成相变材料膜（130）以填充开口。
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公开(公告)号：KR1020100027869A
公开(公告)日：2010-03-11
申请号：KR1020080086959
申请日：2008-09-03
Applicant: 삼성전자주식회사 , 도쿄엘렉트론가부시키가이샤
IPC: H01L21/205 , H01L27/115 , H01L21/8247
CPC classification number: H01L45/124 , C23C16/45531 , C23C16/45546 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/1691 , C23C16/305
Abstract: PURPOSE: A method and an apparatus for forming a phase-change layer and a method for manufacturing a phase-change memory device are provided to improve the composition dispersion of the phase-change layer using a chamber pressure change cycle with an atomic layer deposition method. CONSTITUTION: Source is supplied to a chamber. The source is purged from the chamber. According to the state of the source, the pressure of the chamber is changed. In case of supplying the source into the chamber, a high pressure is set for the chamber. In case of purging the source from the chamber, a low pressure is set for the chamber. A phase-chnge layer with superior composition dispersion is formed.
Abstract translation: 目的：提供一种用于形成相变层的方法和装置以及用于制造相变存储器件的方法，以使用原子层沉积方法改进使用腔室压力变化循环的相变层的组成分散 。 构成：将源提供给室。 源头从腔室中清除。 根据来源的状态，房间的压力发生变化。 在将源供应到室中的情况下，为腔室设定高压。 在从腔室清除源的情况下，为腔室设定低压。 形成具有优异组成分散性的相位层。
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公开(公告)号：KR1020090117103A
公开(公告)日：2009-11-12
申请号：KR1020080043005
申请日：2008-05-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/143 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683 , H01L21/0226
Abstract: PURPOSE: A phase change memory device is provided to perform a multi level cell function by including phase material patterns with different electrical characteristics. CONSTITUTION: A phase change memory device includes a first electrode, a second electrode, a first phase change material pattern(65) and a second phase change material pattern(75). The first phase change material pattern and the second phase change material pattern are interposed between the first electrode and the second electrode. The first and second phase change material patterns. The first phase change material pattern and the second phase change material pattern have different widths.
Abstract translation: 目的：提供相变存储器件以通过包括具有不同电特性的相材料图案来执行多电平单元功能。 构成：相变存储器件包括第一电极，第二电极，第一相变材料图案（65）和第二相变材料图案（75）。 第一相变材料图案和第二相变材料图案介于第一电极和第二电极之间。 第一和第二相变材料图案。 第一相变材料图案和第二相变材料图案具有不同的宽度。
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公开(公告)号：KR1020080080852A
公开(公告)日：2008-09-05
申请号：KR1020070021110
申请日：2007-03-02
Applicant: 삼성전자주식회사
IPC: H01L21/203
CPC classification number: H01L21/02194 , C23C14/35 , H01L21/02266
Abstract: A method for forming a strontium-ruthenium oxide layer is provided to reduce surface resistance in the strontium-ruthenium oxide layer by using a magnetron. A target(130), a wafer(120) on a heating plate(110) facing the target, and a magnetron sputtering device including a magnetron(140) arranged in a backside of the target are provided. A strontium-ruthenium oxide layer is formed by using the magnetron sputtering device. The magnetron includes a rotary magnet and a gravity center scale arranged at one side of the rotary magnet. The rotary magnet includes a concave part. One end of the concave part is composed of a heart-shaped curve.
Abstract translation: 提供了形成锶 - 氧化钌层的方法，以通过使用磁控管来降低锶 - 氧化钌层中的表面电阻。 提供靶（130），面对靶的加热板（110）上的晶片（120），以及包括布置在靶的背面的磁控管（140）的磁控溅射装置。 通过使用磁控溅射装置形成锶 - 氧化钌层。 磁控管包括设置在旋转磁体一侧的旋转磁体和重心刻度。 旋转磁体包括凹部。 凹部的一端由心形曲线构成。
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公开(公告)号：KR1020080019995A
公开(公告)日：2008-03-05
申请号：KR1020060082656
申请日：2006-08-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L27/108
CPC classification number: H01L27/11507 , H01L21/28273 , H01L27/11509
Abstract: A method for manufacturing a semiconductor device including a ferroelectric capacitor is provided to prevent generation of a leakage current from a ferroelectric by curing the damage of the ferroelectric. A lower electrode layer, a ferroelectric layer, and an upper electrode layer are sequentially deposited on a semiconductor substrate(100). A plasma etch process using an etch gas including oxygen and a cleaning gas including fluorine is performed to pattern the upper electrode layer, the ferroelectric layer, and the lower electrode layer, and to form a capacitor as a stacked structure of the lower electrode layer pattern(142), the ferroelectric layer pattern(144), and the upper electrode layer pattern(146). The cleaning gas includes one element selected from a group including F2, SF6, NF3, Si2F6, SiF4, CF4, CHF3, C2F6, C4F8, C5F8, and C3F8.
Abstract translation: 提供一种制造包括铁电电容器的半导体器件的方法，用于通过固化铁电体的损伤来防止从铁电体产生泄漏电流。 在半导体衬底（100）上依次沉积下电极层，铁电体层和上电极层。 执行使用包括氧气和包括氟的清洁气体的蚀刻气体的等离子体蚀刻工艺以对上电极层，铁电层和下电极层进行图案化，并形成作为下电极层图案的层叠结构的电容器 （142），铁电层图案（144）和上电极层图案（146）。 清洁气体包括从包括F2，SF6，NF3，Si2F6，SiF4，CF4，CHF3，C2F6，C4F8，C5F8和C3F8的组中选择的一种元素。
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