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    휴대용 단말기의 안테나 장치
    3.
    发明公开
    휴대용 단말기의 안테나 장치 无效
    天线设备可用端子

    公开(公告)号：KR1020120062121A

    公开(公告)日：2012-06-14

    申请号：KR1020100123231

    申请日：2010-12-06

    Applicant: 삼성전자주식회사

    Inventor： 최종우 ,  이재룡

    IPC: H01Q21/30 ,  H01Q5/00

    CPC classification number: H01Q21/30 ,  H01Q1/2208 ,  H01Q1/243 ,  H01Q1/32

    Abstract: PURPOSE: An antenna device for a portable terminal is provided to improve the speech quality of a portable terminal and to slim the portable terminal. CONSTITUTION: An antenna device(30) for a portable terminal comprises a first antenna(31), a second antenna(32), a module unit, and a control unit. The second antenna has higher resonance frequency than the first antenna. The module unit transmits and receives signals to/from the first and second antennas. The control unit selectively uses the first and second antennas depending on usage environment.

    Abstract translation: 目的：提供便携式终端的天线装置，以提高便携式终端的语音质量并使便携式终端变薄。 构成：用于便携式终端的天线装置（30）包括第一天线（31），第二天线（32），模块单元和控制单元。 第二天线具有比第一天线更高的谐振频率。 模块单元向/从第一和第二天线发送和接收信号。 控制单元根据使用环境有选择地使用第一和第二天线。

    반도체 칩 본딩 장치
    4.
    发明公开
    반도체 칩 본딩 장치 失效
    用于在基板上粘合半导体芯片的装置

    公开(公告)号：KR1020090009641A

    公开(公告)日：2009-01-23

    申请号：KR1020070073095

    申请日：2007-07-20

    Applicant: 삼성전자주식회사

    Inventor： 윤철상 ,  하용대 ,  이재룡 ,  조정순 ,  이범우 ,  김필준

    IPC: H01L23/48 ,  H01L21/60

    CPC classification number: H01L24/95 ,  H01L21/6838 ,  H01L24/28 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/75733 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  Y10T156/17 ,  H01L2924/00

    Abstract: A semiconductor chip bonding device is provided to perform a control operation so that a horizontal state of a semiconductor chip can be maintained on a lead frame, thereby minimizing damage of the semiconductor chip and omitting special horizontality control time when replacing a collet. A semiconductor chip bonding device comprises a chip holding unit(100), a bond head unit(200) and a balance control unit(300). The chip holding unit holds a semiconductor chip(C) to be bonded in a lead frame. The bond head unit is connected with the chip holding unit by the medium of the balance control unit. The bond head unit adds bonding load. The bonding load is delivered through the balance control unit to the chip holding unit. The balance control unit rotates the chip holding unit so that the chip holding unit can be horizontal to the lead frame while delivering the bonding load of the bond head unit. The balance control unit more includes a load transmission member(320) and a connecting member(340). The load transmission member delivers bonding load of a bond head shaft(220) to the chip holding unit. The connecting member connects the load transmission member and the chip holding unit so as to achieve a relative rotation movement of the chip holding unit on the load transmission member when transmitting the bonding load.

    Abstract translation: 提供半导体芯片接合装置以执行控制操作，使得可以在引线框架上保持半导体芯片的水平状态，从而最小化半导体芯片的损坏，并且在更换夹头时省略特殊的水平度控制时间。 半导体芯片接合装置包括芯片保持单元（100），结合头单元（200）和平衡控制单元（300）。 芯片保持单元保持要接合在引线框架中的半导体芯片（C）。 接合头单元通过平衡控制单元的介质与芯片保持单元连接。 粘结头单元增加了粘结载荷。 接合负载通过平衡控制单元输送到芯片保持单元。 平衡控制单元旋转芯片保持单元，使得芯片保持单元可以在输送接合头单元的粘合负载的同时与引线框架水平。 平衡控制单元还包括负载传递部件（320）和连接部件（340）。 负载传递部件将接合头轴（220）的接合负载输送到芯片保持单元。 连接构件连接负载传递构件和芯片保持单元，以便当发送接合负载时实现芯片保持单元在负载传递构件上的相对旋转运动。

    이미지 프로세싱을 이용한 PCB 라인 검출장치
    7.
    发明授权
    이미지 프로세싱을 이용한 PCB 라인 검출장치 失效
    用于处理的PCB线路测试装置

    公开(公告)号：KR1019890002448B1

    公开(公告)日：1989-07-03

    申请号：KR1019860004907

    申请日：1986-06-19

    Applicant: 삼성전자주식회사

    Inventor： 이재룡 ,  이창섭

    IPC: H05K13/08

    Abstract: The apparatus including the CCTV camera and computer utilizes the image process for detecting the line fault of the PCB pattern. The circuit comprises a CCTV camera (10) for accepting the image, a digitizer (20) converting analog signal to discret digital signals, a two-dimensional local shift buffer (30) for converting the output of the digitiser to two-dimensional state, a boundary line detection circuit (40) for optaining only information about the boundary of the pattern line, a small area detecting circuit (50) for detecting the fault area, a comparator (50) for obtaining final PCB pattern line, and an error determination circuit (70).

    Abstract translation: 包括CCTV摄像机和计算机的设备利用图像处理来检测PCB图案的线路故障。 该电路包括用于接收图像的闭路电视摄像机（10），将模拟信号转换为离散数字信号的数字转换器（20），用于将数字转换器的输出转换为二维状态的二维局部移位缓冲器（30） 用于仅选择关于图案线的边界的信息的边界线检测电路（40），用于检测故障区域的小区域检测电路（50），用于获得最终PCB图案线的比较器（50）和误差确定 电路（70）。

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