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公开(公告)号：KR100690924B1
公开(公告)日：2007-03-09
申请号：KR1020050127042
申请日：2005-12-21
Applicant: 삼성전자주식회사
IPC: H01L21/8238 , H01L21/336
Abstract: A semiconductor IC device is provided to simplify a fabricating process and reduce a fabricating cost by decreasing the number of used masks. A substrate(100) is prepared in which a low-voltage transistor region of first conductivity type and a high-voltage transistor region of second conductivity type. A low voltage transistor of first conductivity type includes a first well of second conductivity type, a first gate electrode, a first low density impurity region of second conductivity type and a high-density impurity region of first conductivity type. The first well is formed in the low voltage transistor region. The first gate electrode is formed on the first well. The first low-density impurity region is formed in the first well to adjust a threshold voltage. The high-density impurity region of first conductivity type is aligned with both sides of the first gate electrode. A high voltage transistor of second conductivity type includes a second well of first conductivity type, a second gate electrode and a high voltage transistor of second conductivity type. The second well is formed in the high-voltage transistor region. The second gate electrode is formed on the second well. The high-density impurity region of second conductivity type is formed in the second well, having substantially the same Rp(projected range) as that of the first low-density impurity region for adjusting the threshold voltage and aligned with the second low-density impurity region and both sides of the second gate electrode.
Abstract translation: 提供半导体IC器件以简化制造工艺并通过减少使用的掩模的数量来降低制造成本。 准备衬底（100），其中，第一导电类型的低电压晶体管区域和第二导电类型的高电压晶体管区域。 第一导电类型的低电压晶体管包括第二导电类型的第一阱，第一栅电极，第二导电类型的第一低浓度杂质区域和第一导电类型的高浓度杂质区域。 第一阱形成在低电压晶体管区域中。 第一栅电极形成在第一阱上。 第一低密度杂质区形成在第一阱中以调节阈值电压。 第一导电类型的高浓度杂质区域与第一栅电极的两侧对齐。 第二导电类型的高电压晶体管包括第一导电类型的第二阱，第二栅电极和第二导电类型的高电压晶体管。 第二阱形成在高电压晶体管区域中。 第二栅电极形成在第二阱上。 在第二阱中形成第二导电类型的高浓度杂质区，其具有与用于调节阈值电压的第一低浓度杂质区的Rp（投影范围）基本相同的Rp（投影范围）并且与第二低浓度杂质 区域和第二栅电极的两侧。
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公开(公告)号：KR1020150040182A
公开(公告)日：2015-04-14
申请号：KR1020130132241
申请日：2013-11-01
Applicant: 삼성전자주식회사
IPC: H01L21/265 , H01L21/027
CPC classification number: H01L21/266
Abstract: 반도체장치의제조방법이제공된다. 반도체장치의제조방법은, 기판상에서로다른제1 및제2 하드마스크막을순차적으로형성하고, 상기제2 하드마스크막을제1 식각을통해패터닝하여상기제1 하드마스크막을노출시키고, 상기노출된제1 하드마스크막을상기제1 식각을통해패터닝하여상기기판을노출시키고, 상기노출된기판에이온을주입하고, 상기기판이노출된상태로상기패터닝된제2 및제1 하드마스크막을상기제1 식각과다른제2 식각을통해순차적으로제거하는것을포함한다.
Abstract translation: 提供一种半导体器件的制造方法。 制造半导体器件的方法包括以下步骤：在衬底上顺序地形成不同的第一和第二硬掩模膜; 通过第一次蚀刻第二硬掩模膜，通过图案化曝光第一硬掩模膜; 通过第一蚀刻图案化曝光的第一硬掩模膜来曝光衬底; 向暴露的基底注入离子; 以及通过不同于第一蚀刻的第二蚀刻而暴露基板时，依次去除图案化的第二和第一硬掩模膜。
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公开(公告)号：KR102082626B1
公开(公告)日：2020-02-28
申请号：KR1020130132241
申请日：2013-11-01
Applicant: 삼성전자주식회사
IPC: H01L21/265 , H01L21/027
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