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公开(公告)号：KR101635139B1
公开(公告)日：2016-07-11
申请号：KR1020090093306
申请日：2009-09-30
Applicant: 삼성전자주식회사
IPC: G11C11/15
CPC classification number: G11C11/161
Abstract: 자기메모리소자가제공된다. 이자기메모리소자는, 기판상의터널베리어, 터널베리어의일 면과접하는제1 접합자성층과제1 접합자성층에의해터널베리어와이격되는제1 수직자성층, 터널베리어의다른면과접하는제2 접합자성층과제2 접합자성층에의해터널베리어와이격되는제2 수직자성층, 그리고제1 접합자성층과제1 수직자성층사이의비자성층을포함한다.
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公开(公告)号：KR101566925B1
公开(公告)日：2015-11-16
申请号：KR1020100008756
申请日：2010-01-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/308 , H01L21/8247
CPC classification number: H01L21/28
Abstract: 반도체소자의제조방법을제공한다. 이방법은기판상에하지막을형성하는것을구비한다. 상기하지막 상에희생막을형성한다. 상기희생막을패터닝하여상기하지막의소정영역을노출시키는개구부를형성한다. 상기개구부내에마스크막을형성한다. 상기마스크막의일부또는전부를산화시키어산화물마스크를형성한다. 상기희생막을제거한다. 상기산화물마스크를식각마스크로이용하여상기하지막을식각하여하지막패턴을형성한다.
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公开(公告)号：KR101463948B1
公开(公告)日：2014-11-27
申请号：KR1020100110520
申请日：2010-11-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L43/10 , G11C11/02 , G11C11/16 , G11C11/1675 , H01L27/224 , H01L43/08
Abstract: 자기 기억 소자를 제공한다. 이 소자는 기판 상에 배치된 기준 패턴, 자성 패턴 및 이들 사이의 터널 배리어 패턴을 포함할 수 있다. 또한, 이 소자는 자성 패턴 내부에(inside) 배치된 적어도 하나의 수직 자성부를 포함할 수 있다. 수직 자성부는 자성 패턴의 자화방향에 수직한 자화 성분을 갖는 수직 자성 물질을 포함한다.
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公开(公告)号：KR1020120048989A
公开(公告)日：2012-05-16
申请号：KR1020100110520
申请日：2010-11-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L43/10 , G11C11/02 , G11C11/16 , G11C11/1675 , H01L27/224 , H01L43/08 , H01L43/12 , Y10S977/935
Abstract: PURPOSE: A magnetic memory device is provided to reduce the threshold current density of a magnetism pattern by arranging a perpendicular magnetic part in a magnetism pattern. CONSTITUTION: A first inter layer dielectric layer(103) is formed on a substrate(100). A lower contact plug(105) is arranged in a lower contact hole passing through the first inter layer dielectric layer. A reference pattern(130a) and a magnetism pattern(140a) are arranged on the first inter layer dielectric layer. A tunnel barrier pattern(135a) is interposed between the reference pattern and the magnetism pattern. A first electrode(110a) is interposed between the reference pattern and the first inter layer dielectric layer.
Abstract translation: 目的：提供一种磁存储器件，用于通过将垂直磁性部件布置在磁力图案中来减小磁性图案的阈值电流密度。 构成：在基板（100）上形成第一层间介电层（103）。 下接触插塞（105）布置在穿过第一层间介电层的下接触孔中。 参考图案（130a）和磁性图案（140a）布置在第一层间介电层上。 隧道势垒图案（135a）插入在参考图案和磁图案之间。 第一电极（110a）介于参考图案和第一层间介电层之间。
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公开(公告)号：KR1020110035538A
公开(公告)日：2011-04-06
申请号：KR1020090093306
申请日：2009-09-30
Applicant: 삼성전자주식회사
IPC: G11C11/15
CPC classification number: G11C11/161 , H01L27/222 , H01L43/08 , H01L43/10
Abstract: PURPOSE: A magnetic memory device is provided to improve the magneto-resistance ratio and vertical magnetization property of a magnetic tunnel junction by interposing a nonmagnetic layer between a vertical magnetic layer and a junction magnetic layer. CONSTITUTION: In a magnetic memory device, a tunnel barrier(145) is formed on a substrate(100). A first junction magnetic layer(141) is contacted with one side of the tunnel barrier. The first vertical magnetic layer(123) is separated from the tunnel barrier. A second junction magnetic layer(149) is contacted with one side of the tunnel barrier. The second vertical magnetic layer(163) is separated with the tunnel barrier. A non-magnetic layer(130) is formed between the first junction magnetic layer and the first vertical magnetic layer.
Abstract translation: 目的：提供一种磁存储器件，通过在垂直磁性层和结磁性层之间插入非磁性层来改善磁性隧道结的磁阻比和垂直磁化特性。 构成：在磁存储器件中，在衬底（100）上形成隧道势垒（145）。 第一结磁性层（141）与隧道势垒的一侧接触。 第一垂直磁性层（123）与隧道屏障分离。 第二结磁性层（149）与隧道屏障的一侧接触。 第二垂直磁性层（163）与隧道屏障分离。 在第一结磁性层和第一垂直磁性层之间形成非磁性层（130）。
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Patent Agency Ranking
公开(公告)号：KR100843241B1
公开(公告)日：2008-07-02
申请号：KR1020070031088
申请日：2007-03-29
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/0274 , G03F1/80 , G03F7/70466 , H01L21/32139
Abstract: A method for manufacturing a semiconductor device is provided to form a fine pattern through a simple method using self-aligned double patterning. A first oxide layer pattern(20a) is formed on a silicon substrate. The silicon substrate is etched to a predetermined depth by using the first oxide layer pattern as an etch mask. A first silicon layer pattern is formed on the silicon substrate and the first oxide layer pattern in order to form a groove between the oxide layer patterns. A second oxide layer pattern(40b) having a top surface corresponding to the top surface of the first oxide layer pattern is formed in the groove. A second silicon layer pattern is formed by removing a part of the first silicon layer pattern higher than the top surface of the second oxide layer pattern. A third silicon layer pattern(30c) is formed by heating the second silicon layer pattern.
Abstract translation: 提供一种制造半导体器件的方法，以通过使用自对准双重图案化的简单方法形成精细图案。 在硅衬底上形成第一氧化物层图案（20a）。 通过使用第一氧化物层图案作为蚀刻掩模，将硅衬底蚀刻到预定深度。 在硅衬底和第一氧化物层图案上形成第一硅层图案，以便在氧化物层图案之间形成凹槽。 在沟槽中形成具有与第一氧化物层图案的顶表面对应的顶表面的第二氧化物层图案（40b）。 通过去除比第二氧化物层图案的顶表面高的第一硅层图案的一部分来形成第二硅层图案。 通过加热第二硅层图案形成第三硅层图案（30c）。
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公开(公告)号：KR100839355B1
公开(公告)日：2008-06-19
申请号：KR1020060117987
申请日：2006-11-28
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/02032 , C09G1/02 , H01L21/02024 , H01L21/02079
Abstract: 두 종류의 슬러리를 이용하여 연마하여 기판의 표면을 평탄화시킬 수 있는 기판의 재생 방법에서는 가장자리 영역에 단차가 형성된 기판을 건식 실리카(fumed silica)를 포함하는 슬러리를 사용하여, 상기 단차가 형성된 부분이 제거되도록 1차 화학적 기계적 연마한다. 콜로이드성 실리카(colloidal silica)를 포함하는 슬러리를 사용하여, 상기 기판의 표면 거칠기를 개선하기 위하여 상기 기판을 2차 화학적 기계적 연마한다. 상기 1차 및 2차 화학적 기계적 연마는 폴리우레탄 물질을 포함하는 연마 패드를 이용하여 수행한다. 이때, 상기 가장자리 영역에 상부로 단차가 형성된 기판은 에스오아이(Silicon On Insulator) 기판의 제조 공정에 사용된 도너(donor) 기판이다. 따라서, 상기와 같이 재생된 도너 기판은 이후 반도체 공정에서 다시 재활용할 수 이어 제조공정의 비용을 낮출 수 있다.
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公开(公告)号：KR1020080051269A
公开(公告)日：2008-06-11
申请号：KR1020060122019
申请日：2006-12-05
Applicant: 삼성전자주식회사
IPC: H01L21/8229
Abstract: A method of forming a silicon channel layer and a method of manufacturing a stack memory device are provided to improve the yield of the device by forming the silicon channel layer with minimized thickness distribution variations. A second substrate(126) jointed to a first substrate(100) is prepared, and then a polishing stop layer(130) having polishing selectivity different from a silicon(140) is formed on the second substrate. A silicon layer is formed on the polishing stop layer to cover a damaged edge region of the second substrate at an ion cutting process. The silicon layer is removed by a first chemical mechanical polishing process until the surface of the polishing stop layer is exposed. The polishing stop layer is removed, and then the second substrate is polished by a second chemical mechanical polishing process to form the second substrate as a silicon channel layer of the first substrate.
Abstract translation: 提供一种形成硅沟道层的方法和制造堆叠存储器件的方法，以通过以最小的厚度分布变化形成硅沟道层来提高器件的产量。 准备与第一基板（100）接合的第二基板（126），然后在第二基板上形成具有与硅（140）不同的抛光选择性的抛光停止层（130）。 在离子切割处理中，在抛光停止层上形成硅层以覆盖第二基板的损坏边缘区域。 通过第一化学机械抛光工艺去除硅层，直到抛光停止层的表面露出。 除去抛光停止层，然后通过第二化学机械抛光工艺抛光第二衬底，以形成作为第一衬底的硅沟道层的第二衬底。
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公开(公告)号：KR1020080038535A
公开(公告)日：2008-05-07
申请号：KR1020060105523
申请日：2006-10-30
Applicant: 삼성전자주식회사
IPC: H01L21/20
CPC classification number: H01L21/185 , H01L21/02458 , H01L21/02472 , H01L21/30625 , H01L21/324
Abstract: A method for manufacturing a stack-type semiconductor apparatus is provided to improve the thickness uniformity of a surface layer used as a channel silicon layer by completely removing a polishing sacrificial layer using slurries after forming a polishing stop layer. A first substrate having a surface layer(16) and a second substrate(20) are prepared. A semiconductor structure(25) is formed on the second substrate. A polishing stop layer including oxide or nitride is formed under the surface layer. A separating layer is formed under the polishing stop layer by using a hydrogen ion implantation. The first substrate and the second substrate are joined to each other so that the surface layer is contacted to the semiconductor structure. A bulk layer of the first substrate is separated from the second substrate by using the separating layer as a cutting surface. A CMP process is performed until the polishing stop layer of the joined first substrate is exposed. The polishing stop layer is removed so that the surface layer of the joined first substrate is exposed.
Abstract translation: 提供一种叠层型半导体装置的制造方法，用于通过在形成抛光停止层之后通过使用浆料完全去除抛光牺牲层来改善用作沟道硅层的表面层的厚度均匀性。 制备具有表面层（16）和第二衬底（20）的第一衬底。 半导体结构（25）形成在第二基板上。 包含氧化物或氮化物的抛光停止层形成在表面层下面。 通过使用氢离子注入在抛光停止层下形成分离层。 第一基板和第二基板彼此接合，使得表面层与半导体结构接触。 通过使用分离层作为切割表面，将第一基板的本体层与第二基板分离。 进行CMP处理，直到接合的第一基板的抛光停止层露出。 去除抛光停止层，使得接合的第一基板的表面层露出。
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10.发明授权
公开(公告)号：KR100791074B1
公开(公告)日：2008-01-02
申请号：KR1020060080005
申请日：2006-08-23
Applicant: 삼성전자주식회사
IPC: H01L21/28 , H01L27/105 , H01L21/3205
CPC classification number: H01L27/11507 , H01L27/11502 , H01L28/57
Abstract: A contact structure having a barrier layer containing noble metal, a ferroelectric random access memory device employing the same, and a method for fabricating the same are provided to prevent a lowering effect of polarization characteristics of ferroelectric capacitors by using a noble metal barrier. An interlayer dielectric(116) is formed on an upper surface of a semiconductor substrate(100). A plurality of contact plug(118s',118s",118d) are electrically connected through the interlayer dielectric to the semiconductor substrate. A lower barrier pattern is formed to surround a sidewall and a lower surface of the contact plug. An upper barrier pattern comes in contact with an upper surface of the contact plug. The lower barrier pattern and the upper barrier pattern include noble metal. The contact plug is formed with tungsten.
Abstract translation: 提供具有含有贵金属的阻挡层的接触结构体，使用其的铁电随机存取存储器件及其制造方法，以通过使用贵金属阻挡层来防止强电介质电容器的极化特性的降低效果。 在半导体衬底（100）的上表面上形成层间电介质（116）。 多个接触插塞（118s'，118s“，118d）通过层间电介质电连接到半导体衬底，形成下阻挡图案以围绕接触插塞的侧壁和下表面，上阻挡图案 与接触塞的上表面接触，下阻挡图案和上阻挡图案包括贵金属，接触塞由钨形成。
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