公开(公告)号：KR100500439B1

公开(公告)日：2005-07-12

申请号：KR1020020048267

申请日：2002-08-14

Applicant: 삼성전자주식회사

Inventor： 이창헌 ,  정문모 ,  김욱제

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

Abstract: 게이트 스페이서가 포지티브 슬로프를 갖는 반도체 장치의 제조방법이 제공된다. 상기 반도체 장치의 제조방법은 반도체 기판상에 다수의 게이트를 형성하는 것을 포함한다. 상기 게이트를 갖는 기판의 전면 상에 제1 절연막 및 상기 제1 절연막과 습식식각차를 갖는 제2 절연막을 차례로 형성한다. 상기 제2 절연막 및 제1 절연막을 식각하여 상기 게이트의 측벽에 게이트 스페이서를 형성한다. 다음으로, 상기 게이트 스페이서를 갖는 결과물에 대한 세정공정을 수행하여 상기 게이트 스페이서의 에지부분에 포지티브 슬로프를 형성한다. 상기 게이트 사이가 채워지도록 상기 기판상에 폴리실리콘막을 형성한다. 이어서, 상기 폴리실리콘막중 일부를 식각하여 상기 기판을 노출시키는 개구부를 형성한다. 상기 개구부가 채워지도록 상기 노출된 기판상에 층간절연막을 형성한다.

公开(公告)号：KR1020040013293A

公开(公告)日：2004-02-14

申请号：KR1020020046151

申请日：2002-08-05

Applicant: 삼성전자주식회사

Inventor： 이창헌 ,  정문모 ,  윤재만

IPC: H01L27/10

Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to simplify a fabricating process by simultaneously forming contacts in a cell region and a peripheral circuit/core region while performing a photolithography process once. CONSTITUTION: An isolation layer(210) is formed in a semiconductor substrate(200) which is divided into the cell region(201) and the peripheral circuit/core region(202). A gate(220) including a capping layer and a spacer is formed on the semiconductor substrate. A polysilicon layer is formed on the substrate between the gates, separated by the gates. The polysilicon layer on the isolation layer is etched to form an opening. The opening is gap-filled with the first interlayer dielectric. The polysilicon layer is silicidated to form a silicide layer(255). The second interlayer dielectric is formed on the substrate. The contacts(291,293,295) are formed to expose the silicide layer on the cell region, the gate and the substrate in the peripheral circuit/core region.

Abstract translation: 目的：提供一种制造半导体器件的方法，以在一次执行光刻处理的同时在单元区域和外围电路/芯区域中同时形成接触来简化制造工艺。 构成：隔离层（210）形成在半导体衬底（200）中，半导体衬底（200）被分成单元区域（201）和外围电路/核心区域（202）。 在半导体衬底上形成包括覆盖层和间隔物的栅极（220）。 在门之间的基板上形成多晶硅层，由栅极分开。 蚀刻隔离层上的多晶硅层以形成开口。 开口用第一层间电介质填充。 多晶硅层被硅化以形成硅化物层（255）。 在基板上形成第二层间电介质。 形成触点（291,293,295）以暴露外围电路/芯区域中的单元区域，栅极和基板上的硅化物层。

公开(公告)号：KR1020020068417A

公开(公告)日：2002-08-27

申请号：KR1020010008755

申请日：2001-02-21

Applicant: 삼성전자주식회사

Inventor： 정문모

IPC: H01L21/28

CPC classification number: H01L21/76849 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76865

Abstract: PURPOSE: A method for fabricating a semiconductor device with a contact having uniform contact resistance is provided to form uniform contact resistance regarding the entire surface of a semiconductor substrate, by making the bottom surface of a contact hole connecting a lower interconnection layer with an upper interconnection layer positioned on or inside a capping layer located on the lower interconnection. CONSTITUTION: The semiconductor substrate(50) is prepared. An interconnection layer(54), a capping layer(56a) and an etch stop layer(58a) are sequentially formed in a part of the upper surface of the semiconductor substrate. An interlayer dielectric including the first contact hole exposing a partial surface of the etch stop layer is formed on the semiconductor substrate having the etch stop layer, composed of a material having high etch selectivity regarding the etch stop layer. The etch stop layer exposed by the first contact hole is completely eliminated to form the second contact hole exposing the upper surface of the capping layer. A conductive layer(66) filling the second contact hole is formed.

Abstract translation: 目的：提供一种制造具有均匀接触电阻的触点的半导体器件的方法，以通过使下部互连层与上部互连件的接触孔的底面形成关于半导体基板的整个表面的均匀的接触电阻 层位于下部互连上的覆盖层上或内侧。 构成：制备半导体衬底（50）。 在半导体衬底的上表面的一部分中依次形成互连层（54），覆盖层（56a）和蚀刻停止层（58a）。 包括暴露蚀刻停止层的部分表面的第一接触孔的层间电介质形成在具有蚀刻停止层的半导体衬底上，该蚀刻停止层由对蚀刻停止层具有高蚀刻选择性的材料构成。 完全消除由第一接触孔暴露的蚀刻停止层，以形成露出覆盖层的上表面的第二接触孔。 形成填充第二接触孔的导电层（66）。

公开(公告)号：KR100448719B1

公开(公告)日：2004-09-13

申请号：KR1020020063979

申请日：2002-10-18

Applicant: 삼성전자주식회사

Inventor： 정문모 ,  이창헌

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/31116 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885

Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.

Abstract translation: 根据本发明实施例的半导体器件及其制造方法包括：准备具有第一接触焊盘和第二接触焊盘的半导体衬底; 在衬底上形成第一绝缘膜; 刻蚀所述第一绝缘膜以形成分别暴露所述第一接触焊盘和所述第二接触焊盘的凹槽形位线图案和接触件; 同时分别在触点和位线图案中形成接触插塞和位线，接触插塞和位线具有共面的上表面; 以及形成连接到第一接触垫的电容器的底部电极。

公开(公告)号：KR100400035B1

公开(公告)日：2003-09-29

申请号：KR1020010008755

申请日：2001-02-21

Applicant: 삼성전자주식회사

Inventor： 정문모

IPC: H01L21/28

CPC classification number: H01L21/76849 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76865

Abstract: A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same are provided. An interconnection layer, a capping layer, and an etching stopper are sequentially formed on a semiconductor substrate. An interlayer insulating layer is deposited over the resulting structure. The etching stopper is formed of a material having a high etching selectivity with respect to the interlayer insulating layer. Then a first contact hole is formed to expose the surface of the etching stopper by etching a predetermined portion of the interlayer insulating layer. Either the etching stopper exposed by the first contact hole or the etching stopper exposed by the first contact hole and part of the capping layer are etched to form a second contact hole. As a result, it is possible to manufacture a semiconductor device having uniform contact resistance over the surface of the semiconductor substrate, irrespective of topology of a lower interconnection layer or the degree of flatness of the interlayer insulating layer covering the lower interconnection layer.

Abstract translation: 提供了一种具有能够保持连接多层互连的触点的接触电阻的接触孔的半导体器件及其制造方法。 在半导体衬底上顺序地形成互连层，覆盖层和蚀刻终止层。 层间绝缘层沉积在所得结构上。 蚀刻停止层由相对于层间绝缘层具有高蚀刻选择性的材料形成。 然后，通过蚀刻层间绝缘层的预定部分，形成第一接触孔以暴露蚀刻停止层的表面。 蚀刻由第一接触孔暴露的蚀刻阻挡层或由第一接触孔暴露的蚀刻阻挡层和部分覆盖层以形成第二接触孔。 结果，无论下互连层的拓扑结构或覆盖下互连层的层间绝缘层的平坦度如何，都可以制造在半导体衬底的表面上具有均匀接触电阻的半导体器件。

公开(公告)号：KR1020040035213A

公开(公告)日：2004-04-29

申请号：KR1020020063979

申请日：2002-10-18

Applicant: 삼성전자주식회사

Inventor： 정문모 ,  이창헌

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/31116 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885

Abstract: PURPOSE: A semiconductor device using a damascene process and a manufacturing method thereof are provided to be capable of conserving the insulation characteristic between a bit line and a storage node contact and improving process margin. CONSTITUTION: The first insulating layer is formed on the entire surface of a semiconductor substrate, wherein the semiconductor substrate includes the first and second contact pad(231,235). A contact hole(261) and a groove type bit line pattern(265) are formed by selectively etching the first insulating layer for exposing the first and second contact pad. A contact plug(281) and a bit line(285) are simultaneously formed in the contact hole and the bit line pattern. A lower storage node of a capacitor is formed at the predetermined portion of the resultant structure for being connected with the first contact pad.

Abstract translation: 目的：提供一种使用镶嵌工艺的半导体器件及其制造方法，以能够节省位线与存储节点接触之间的绝缘特性并提高加工余量。 构成：第一绝缘层形成在半导体衬底的整个表面上，其中半导体衬底包括第一和第二接触焊盘（231,235）。 通过选择性地蚀刻用于暴露第一和第二接触焊盘的第一绝缘层来形成接触孔（261）和凹槽型位线图案（265）。 在接触孔和位线图案中同时形成接触插塞（281）和位线（285）。 电容器的下部存储节点形成在所得结构的预定部分处以与第一接触焊盘连接。

公开(公告)号：KR1020040017982A

公开(公告)日：2004-03-02

申请号：KR1020020050244

申请日：2002-08-23

Applicant: 삼성전자주식회사

Inventor： 정문모 ,  요시다마코토

IPC: H01L21/3205

Abstract: PURPOSE: A semiconductor device having a bit line by a damascene process and a manufacturing method thereof are provided to be capable of preventing the bridge phenomenon between bit lines due to tungsten residues and restraining the short phenomenon between a buried contact poly layer and the bit line. CONSTITUTION: A semiconductor device is provided with a semiconductor substrate having an active and inactive region(100,100-1), gates, a gate spacer formed at both sidewalls of each gate, pad contacts(230) formed on the first insulating layer(180), and the second and third insulating layer(240,270-1) sequentially formed at the upper portion of the resultant structure. The semiconductor device further includes bit lines(320-1), grooves having a larger width than that of the bit line, the second nitride layer(350-1) for covering the bit line, the fourth insulating layer(420) and the third nitride layer(440) sequentially formed at the upper portion of the resultant structure, and buried contact poly layers(460) formed at the predetermined upper portions of the resultant structure.

Abstract translation: 目的：提供一种通过镶嵌工艺具有位线的半导体器件及其制造方法，其能够防止由于钨残留引起的位线之间的桥接现象，并且抑制埋入接触多晶硅层与位线之间的短路现象 。 构造：半导体器件设置有具有有源和非活性区域（100,100-1）的半导体衬底，栅极，形成在每个栅极的两个侧壁处的栅极间隔件，形成在第一绝缘层（180）上的焊盘触点（230） 以及顺序地形成在所得结构的上部的第二和第三绝缘层（240,270-1）。 半导体器件还包括位线（320-1），具有比位线的宽度大的沟槽，用于覆盖位线的第二氮化物层（350-1），第四绝缘层（420）和第三绝缘层 在所得结构的上部顺序地形成氮化物层（440），以及形成在所得结构的预定上部的掩埋接触多层（460）。

公开(公告)号：KR1020040016070A

公开(公告)日：2004-02-21

申请号：KR1020020048267

申请日：2002-08-14

Applicant: 삼성전자주식회사

Inventor： 이창헌 ,  정문모 ,  김욱제

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

Abstract: PURPOSE: A method for fabricating a semiconductor device with a gate spacer of a positive slope is provided to prevent a bridge from being generated by residual polysilicon by forming a positive slope in a gate spacer while using a wet etch difference of a spacer insulation layer. CONSTITUTION: A plurality of gates are formed on a semiconductor substrate. A gate spacer is formed so as to have a positive slope at the edge of the gate. A polysilicon layer(240) is formed on the substrate to fill a gap between the gates. A part of the polysilicon layer is etched to form an opening exposing the substrate. An interlayer dielectric(260) is formed on the exposed substrate so as to fill the opening.

Abstract translation: 目的：提供一种用于制造具有正斜率的栅极间隔物的半导体器件的方法，以通过在使用间隔绝缘层的湿蚀刻差的栅极间隔物中形成正斜率来防止由剩余多晶硅产生桥。 构成：在半导体衬底上形成多个栅极。 栅极间隔物形成为在栅极的边缘处具有正斜率。 在衬底上形成多晶硅层（240）以填充栅极之间的间隙。 蚀刻多晶硅层的一部分以形成露出衬底的开口。 在暴露的基板上形成层间电介质（260），以填充开口。

公开(公告)号：KR100439038B1

公开(公告)日：2004-07-03

申请号：KR1020020050246

申请日：2002-08-23

Applicant: 삼성전자주식회사

Inventor： 정문모 ,  이창헌 ,  요시다마코토

IPC: H01L21/3205

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10885

Abstract: Semiconductor device comprises an insulating film formed on a semiconductor substrate having a bit line contact and a bit line pattern, a bit line surrounded by the insulating film, and a bit line covering layer protruding from the insulating film. The protruding section of the bit line covering layer is wider than the width of the bit line. An Independent claim is also included for a process for the production of the semiconductor device.

Abstract translation: 半导体器件包括形成在具有位线接触和位线图案的半导体衬底上的绝缘膜，由绝缘膜围绕的位线以及从绝缘膜突出的位线覆盖层。 位线覆盖层的突出部分比位线的宽度宽。 独立权利要求也包括在用于生产半导体器件的工艺中。

公开(公告)号：KR1020040022043A

公开(公告)日：2004-03-11

申请号：KR1020020053864

申请日：2002-09-06

Applicant: 삼성전자주식회사

Inventor： 정문모 ,  이창헌 ,  김욱제

IPC: H01L27/10

Abstract: PURPOSE: A method for forming a capacitor of a semiconductor device is provided to enhance capacitance by using a nitride layer as an etch stop layer. CONSTITUTION: Bit lines(12) are formed on a semiconductor substrate(10) defined by a cell region and a peripheral region. A nitride layer(14) is formed on the resultant structure. A contact(C) is formed through an interlayer dielectric and a barrier(18) is formed between the cell and peripheral region. A capacitor oxide layer(20) is formed on the resultant structure. A lower electrode(22) is formed by selectively etching the capacitor oxide layer. The lower electrode and contact are exposed by etching the exposed capacitor oxide layer and the interlayer dielectric of the cell region using the nitride layer as an etch stop layer. Then, a dielectric film(24) and an upper electrode(26) are sequentially formed on the exposed lower electrode and the contact.

Abstract translation: 目的：提供一种用于形成半导体器件的电容器的方法，以通过使用氮化物层作为蚀刻停止层来增强电容。 构成：位线（12）形成在由单元区域和外围区域限定的半导体衬底（10）上。 在所得结构上形成氮化物层（14）。 通过层间电介质形成触点（C），并且在电池和周边区域之间形成阻挡层（18）。 在所得结构上形成电容器氧化物层（20）。 通过选择性地蚀刻电容器氧化物层来形成下电极（22）。 通过使用氮化物层作为蚀刻停止层来蚀刻暴露的电容器氧化物层和电池区域的层间电介质来暴露下部电极和接触。 然后，在暴露的下电极和触点上依​​次形成电介质膜（24）和上电极（26）。