公开(公告)号：KR1020090078549A

公开(公告)日：2009-07-20

申请号：KR1020080004433

申请日：2008-01-15

Applicant: 삼성전자주식회사

Inventor： 김용일 ,  홍형선 ,  요시다마코토

IPC: H01L21/76 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L27/105 ,  H01L21/823481 ,  H01L27/0207 ,  H01L21/762 ,  H01L21/823437

Abstract: A manufacturing method of a semiconductor device including an isolation process is provided to reduce a depth of an isolation pattern by applying a bias to a conductive pattern included in the isolation pattern. A plurality of isolation patterns including conductive patterns(14a) are formed on an upper surface of a semiconductor substrate(10). A gap(19) is formed between the isolation patterns. An active pattern(20) is formed on the semiconductor substrate in order to bury the gap formed between the isolation patterns. A gate insulating layer(22) is formed on an upper surface of the isolation pattern and an upper surface of the active pattern. A gate pattern(24) is formed on an upper surface of the gate insulating layer.

Abstract translation: 提供了包括隔离工艺的半导体器件的制造方法，以通过向包括在隔离图案中的导电图案施加偏压来减小隔离图案的深度。 在半导体衬底（10）的上表面上形成包括导电图案（14a）的多个隔离图案。 在隔离图案之间形成间隙（19）。 在半导体衬底上形成有源图案（20），以便掩埋形成在隔离图案之间的间隙。 栅极绝缘层（22）形成在隔离图案的上表面和活性图案的上表面上。 栅极图案（24）形成在栅极绝缘层的上表面上。

公开(公告)号：KR1020050027781A

公开(公告)日：2005-03-21

申请号：KR1020030064153

申请日：2003-09-16

Applicant: 삼성전자주식회사

Inventor： 윤재만 ,  박동건 ,  진교영 ,  요시다마코토 ,  박태서

IPC: H01L27/092

CPC classification number: H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

Abstract: A dual gate FET(Field Effect Transistor) and a manufacturing method thereof are provided to prevent the degradation of electrical properties by forming thickly a non-channel gate oxide layer on predetermined portions of a silicon substrate. A plurality of fins(102) are protruded from a silicon substrate(100b) of an active region, wherein each fin has a first and second side. A source and drain region are formed at both edges of the fin. A channel region is formed in the fin. A channel gate oxide layer(180) is formed on the first and second sides of the fin. A pad insulating pattern(110a) is formed on the fin. An isolation pattern(170a) is filled in a trench isolation region. A non-channel gate oxide layer(106a) is formed between the fins on the substrate. A gate line(190) is formed on the resultant structure.

Abstract translation: 提供双栅极FET（场效应晶体管）及其制造方法，以通过在硅衬底的预定部分上形成非沟道栅氧化层来防止电性能的劣化。 多个翅片（102）从有源区的硅基板（100b）突出，其中每个翅片具有第一和第二侧。 源极和漏极区域形成在鳍片的两个边缘处。 在翅片中形成沟道区域。 在鳍片的第一和第二侧上形成沟道栅氧化层（180）。 在翅片上形成焊盘绝缘图案（110a）。 隔离图案（170a）填充在沟槽隔离区域中。 在基板上的翅片之间形成非沟道栅氧化层（106a）。 在所得结构上形成栅极线（190）。

公开(公告)号：KR101416318B1

公开(公告)日：2014-07-09

申请号：KR1020080004433

申请日：2008-01-15

Applicant: 삼성전자주식회사

Inventor： 김용일 ,  홍형선 ,  요시다마코토

IPC: H01L21/76 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L27/105 ,  H01L21/823481 ,  H01L27/0207

Abstract: 본 발명의 반도체 장치의 제조방법은 반도체 기판 상에 도전 패턴을 포함하는 소자 분리 패턴을 복수개 형성하고, 소자 분리 패턴들 사이에 갭을 형성한다. 이어서, 반도체 기판 상에 갭을 매립하는 액티브 패턴을 형성한다. 소자 분리 패턴 및 액티브 패턴 상에 게이트 절연막을 형성한다. 게이트 절연막 상에 게이트 패턴을 형성한다. 소자 분리 패턴은 상기 반도체 기판 상에 형성된 제1 절연 패턴과, 상기 제1 절연 패턴 상에 형성된 상기 도전 패턴과, 상기 도전 패턴의 양측벽에 형성된 제2 절연 패턴이고, 상기 도전 패턴은 상기 제1 절연 패턴, 상기 제2 절연 패턴 및 상기 게이트 절연막에 의하여 둘러싸진다.

公开(公告)号：KR1020100110593A

公开(公告)日：2010-10-13

申请号：KR1020090029012

申请日：2009-04-03

Applicant: 삼성전자주식회사

Inventor： 요시다마코토 ,  홍형선 ,  염계희

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

Abstract: 반도체장치및 그의형성방법을제공할수 있다. 이를위해서, 반도체기판상에셀 비트라인패턴및 주변게이트패턴을형성할수 있다. 상기셀 비트라인패턴은반도체기판의셀 활성영역주변의비활성영역상에배치될수 있다. 상기주변게이트패턴은반도체기판의주변활성영역상에배치될수 있다. 상기셀 비트라인패턴및 셀활성영역사이에셀 콘택플러그를형성할수 있다. 상기주변게이트패턴의측부에위치하도록주변활성영역상에주변콘택플러그가배치될수 있다. 상기셀 비트라인패턴, 주변게이트패턴, 셀및 주변콘택플러그들의상면들을실질적으로동일레벨에서노출시키는절연막이배치될수 있다.

Abstract translation: 目的：提供一种半导体器件及其形成方法，以减小电池接触插头的部件之间的寄生电容。 构成：半导体器件（233）包括无效区域，第一上部布线，第一接触插塞和第二下部布线。 无源区域限制半导体器件的第一和第二有源区域。 第一上部布线布置在第一活动区域周围的非活动区域上。 第一接触插塞的上侧具有与第一上布线的上侧相同的高度，并与第一有源区和第一上布线接触。 第二下部布线的上侧具有与第一接触插塞相同的高度，并且布置在第二有源区域上。 单元阵列区域包括单元栅极图案（59）和单元位线图案（82,86）。 单元有源区（6）位于单元位线图案之间。 在电池活动区域的中心区域上形成电池接触孔（151）。

公开(公告)号：KR1020090108452A

公开(公告)日：2009-10-15

申请号：KR1020080033874

申请日：2008-04-11

Applicant: 삼성전자주식회사

Inventor： 김용일 ,  요시다마코토

IPC: H01L21/28

CPC classification number: H01L27/10855 ,  H01L27/10888

Abstract: PURPOSE: A manufacturing method of a semiconductor device is provided to reduce an electrical short between a landing pass and a recess contact plug in an integrated semiconductor device by increasing a separation distance between the landing pass and the recess contact plug. CONSTITUTION: Gate lines(108) are formed on a semiconductor substrate(101). An interlayer insulation film(110,128) insulates the gate lines. A first contact plug(114) and a second contact plug penetrate the interlayer insulation film, and are formed on the semiconductor substrate between the gate lines. A landing pad(122) is formed on the interlayer insulation film and the first contact plug, and is overlapped with a part of the first contact plug. A recess contact plug(126) is formed by etching the second contact plug.

Abstract translation: 目的：提供一种半导体器件的制造方法，以通过增加层叠通道和凹陷接触插塞之间的间隔距离来减小集成半导体器件中的层叠通孔和凹部接触插塞之间的电短路。 构成：栅极线（108）形成在半导体衬底（101）上。 层间绝缘膜（110,128）绝缘栅极线。 第一接触插塞（114）和第二接触插塞穿透层间绝缘膜，并且形成在栅极线之间的半导体衬底上。 在层间绝缘膜和第一接触插塞上形成着接垫（122），与第一接触插塞的一部分重叠。 通过蚀刻第二接触插塞形成凹部接触插塞（126）。

公开(公告)号：KR1020090080372A

公开(公告)日：2009-07-24

申请号：KR1020080006281

申请日：2008-01-21

Applicant: 삼성전자주식회사

Inventor： 정경호 ,  요시다마코토 ,  강재록 ,  이철 ,  문준석 ,  이철규 ,  조성일

IPC: H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823425 ,  H01L21/82385

Abstract: A method for manufacturing a semiconductor device for reducing a thermal budget to impurity regions of a peripheral circuit region is provided to improve characteristics of the semiconductor device by forming a peripheral transistor after performing a high-temperature process. A substrate(110) including a cell array region and a peripheral circuit region is prepared. The cell array region includes a cell activation region(112c). The peripheral circuit region includes peripheral activation regions(112a,112b). A cell gate pattern(126a) and a peripheral gate pattern(126b) are formed across the cell activation region and the peripheral activation region. A plurality of first cell impurity regions(130c) are formed in the cell activation regions of both sides of the cell gate pattern. A cell bottom interlayer dielectric(136) and a peripheral insulating layer are formed on the substrate in order to cover the cell array region and the peripheral circuit region, respectively. A plurality of cell conductive pads(144c) are formed through the cell bottom interlayer dielectric in order to be electrically connected with the first cell impurity regions. The peripheral insulating layer is removed to expose the peripheral activation regions of both sides of the peripheral gate pattern.

Abstract translation: 提供一种用于制造用于将热量预算减少到外围电路区域的杂质区域的半导体器件的方法，以通过在执行高温处理之后形成外围晶体管来改善半导体器件的特性。 准备包括单元阵列区域和外围电路区域的基板（110）。 电池阵列区域包括电池激活区域（112c）。 外围电路区域包括外围激活区域（112a，112b）。 在单元激活区域和周边激活区域之间形成单元栅极图案（126a）和外围栅极图案（126b）。 在单元栅极图案的两侧的单元激活区域中形成多个第一单元杂质区（130c）。 为了覆盖电池阵列区域和外围电路区域，在基板上形成电池底层间电介质（136）和外围绝缘层。 通过电池底层间电介质形成多个电池导电焊盘（144c），以便与第一电池杂质区域电连接。 去除外围绝缘层以露出外围栅极图案两侧的外围激活区域。

公开(公告)号：KR100814391B1

公开(公告)日：2008-03-18

申请号：KR1020060098380

申请日：2006-10-10

Applicant: 삼성전자주식회사

Inventor： 이철 ,  박동건 ,  양원석 ,  요시다마코토

IPC: G11C11/40 ,  G11C11/4094 ,  G11C11/4074

CPC classification number: G11C11/404 ,  G11C11/4076 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/7851

Abstract: A method of operating a DRAM device including a FIN transistor and a DRAM device thereof are provided to increase integration density of the DRAM device without comprising a generator to apply a body bias to a peri/core region of the DRAM device and thus to reduce operation failure. A semiconductor substrate(100) comprises a FIN active region formed with a FIN transistor, an isolation region and an active region connected to a body part of the FIN transistor as having a flat plane. A gate structure is formed on the center of the FIN active region. A dummy gate structure is formed at the edge of the FIN active region. A source/drain(108) are formed below the surface of the FIN active region on both sides of the gate structure. A first interlayer insulation film(110) covers the gate structure and the dummy gate structure. A bit line structure is electrically connected to the drain. A second interlayer insulation film(114) covers the bit line structure. A capacitor structure(130) is electrically connected to the source. A third interlayer insulation film(120) covers the capacitor. A line structure is connected to the active region surface and the dummy gate structure at the same time, and is connected to a port applied with a ground level from the outside to ground the body of the FIN transistor.

Abstract translation: 提供了一种操作包括FIN晶体管及其DRAM器件的DRAM器件的方法，以增加DRAM器件的集成密度，而不包括发生器，以将体偏置施加到DRAM器件的周边/核心区域，从而减少操作 失败。 半导体衬底（100）包括由FIN晶体管形成的FIN有源区，隔离区和与FIN晶体管的主体部分连接的有源区具有平坦平面。 栅极结构形成在FIN有源区域的中心。 在FIN活性区域的边缘处形成虚拟栅极结构。 源极/漏极（108）形成在栅极结构两侧的FIN有源区的表面下方。 第一层间绝缘膜（110）覆盖栅极结构和虚拟栅极结构。 位线结构电连接到漏极。 第二层间绝缘膜（114）覆盖位线结构。 电容器结构（130）电连接到源极。 第三层间绝缘膜（120）覆盖电容器。 线结构同时连接到有源区表面和伪栅极结构，并且从外部连接到施加有地电平的端口，从而将FIN晶体管的本体接地。

公开(公告)号：KR100739653B1

公开(公告)日：2007-07-13

申请号：KR1020060043169

申请日：2006-05-13

Applicant: 삼성전자주식회사

Inventor： 김근남 ,  요시다마코토

IPC: H01L21/336

Abstract: A fin field effect transistor and a manufacturing method thereof are provided to reduce off current and gate induced drain leakage by extending an effective distance between a source and a drain. An active pin(118) having a round trench(114) on an upper surface. A gate insulation film is formed on a surface of the active fin. A gate electrode(122) is formed in an inner surface of the trench, and has a line width narrower than an upper width of the trench. Impurity regions are formed under the surface of the active fin at both sides of the gate electrode. The trench extends to edges of both sides of the active fin in a first direction perpendicular to a longitudinal direction of the active fin.

Abstract translation: 提供鳍式场效应晶体管及其制造方法，以通过延长源极和漏极之间的有效距离来减少截止电流和栅极感应漏极泄漏。 主动销（118）在上表面上具有圆形沟槽（114）。 栅极绝缘膜形成在有源鳍片的表面上。 栅电极（122）形成在沟槽的内表面中，并具有比沟槽的上宽度窄的线宽。 杂质区域在栅电极两侧的有源鳍片的表面下方形成。 沟槽在垂直于有源鳍的纵向的第一方向上延伸到有源鳍的两侧的边缘。

公开(公告)号：KR101565797B1

公开(公告)日：2015-11-05

申请号：KR1020090012599

申请日：2009-02-16

Applicant: 삼성전자주식회사

Inventor： 윤재만 ,  진교영 ,  홍형선 ,  요시다마코토 ,  김봉수

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76834 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 본발명은, 기판의활성영역과의우수한전기적접촉을제공할수 있는콘택플러그를포함하는반도체장치를개시한다. 본발명의일실시예에따른반도체장치는, 제1 영역과제2 영역이정의된반도체층; 반도체층 상에형성되고, 제1 영역과전기적으로연결된제1 콘택플러그; 반도체층 상에형성되고, 제2 영역과전기적으로연결된제2 콘택플러그; 제1 콘택플러그와전기적으로연결된도전층; 및도전층과제2 콘택플러그를서로절연하도록, 도전층과제2 콘택플러그의사이에위치하고, 도전층의측면및 바닥면일부와대면하는절연층;을포함한다.

公开(公告)号：KR100675288B1

公开(公告)日：2007-01-29

申请号：KR1020050105646

申请日：2005-11-04

Applicant: 삼성전자주식회사

Inventor： 장세명 ,  강재록 ,  성현주 ,  김희중 ,  요시다마코토 ,  전창훈

IPC: H01L21/336

Abstract: A method for manufacturing a semiconductor device and the semiconductor device manufactured thereby are provided to improve a current driving capability and to enhance the degree of integration by using multi-channel transistors. An isolation layer for defining an active region is formed on a semiconductor substrate. A plurality of pre-semiconductor pillars are formed within the active region. The pre-semiconductor pillars are self-aligned with the active region and spaced apart from each other. Semiconductor pillars(180,185,190a,190b) are formed on the resultant structure by etching selectively the pre-semiconductor pillars. Each semiconductor pillar has a hole. At least one gate structure(320a to 320c) are formed on the resultant structure to cross over the semiconductor pillars and the holes of the semiconductor pillars.

Abstract translation: 提供一种用于制造半导体器件的方法和由此制造的半导体器件，以提高电流驱动能力并通过使用多沟道晶体管来提高集成度。 用于限定有源区的隔离层形成在半导体衬底上。 多个预制半导体柱形成在有源区内。 前置半导体柱与有源区自对准并彼此间隔开。 半导体柱（180,185,190a，190b）通过选择性蚀刻前半导体柱而形成在所得结构上。 每个半导体柱都有一个孔。 在所得结构上形成至少一个栅极结构（320a至320c）以跨过半导体柱和半导体柱的孔。