公开(公告)号：KR1020050022075A

公开(公告)日：2005-03-07

申请号：KR1020030059100

申请日：2003-08-26

Applicant: 삼성전자주식회사

Inventor： 정연운

IPC: H01L27/115

Abstract: PURPOSE: A method for fabricating a flash memory device having a high voltage gate insulation layer and a trench isolation layer is provided to prevent a high voltage gate insulation layer from decreasing in quality during a process for forming a trench isolation layer by forming the trench isolation layer before the high voltage gate insulation layer is formed. CONSTITUTION: A trench isolation layer is formed on a semiconductor substrate(200) to define the first and second regions. A high voltage gate insulation layer(208) is formed on the semiconductor substrate in the first region. A low voltage gate insulation layer(218) is formed on the semiconductor substrate in the second region. The low voltage gate insulation layer and the high voltage gate insulation layer are covered with a floating gate electrode layer. An insulation layer is formed on the floating gate electrode layer. A control gate electrode layer is formed on the insulation layer.

Abstract translation: 目的：提供一种制造具有高压栅极绝缘层和沟槽隔离层的闪速存储器件的方法，以防止在通过形成沟槽隔离来形成沟槽隔离层的工艺期间高电压栅极绝缘层的质量降低 在形成高压栅极绝缘层之前的层。 构成：在半导体衬底（200）上形成沟槽隔离层以限定第一和第二区域。 在第一区域中的半导体衬底上形成高压栅极绝缘层（208）。 在第二区域中的半导体衬底上形成低压栅极绝缘层（218）。 低压栅极绝缘层和高压栅极绝缘层被浮栅电极层覆盖。 在浮栅电极层上形成绝缘层。 在绝缘层上形成控制栅电极层。

公开(公告)号：KR1020040033774A

公开(公告)日：2004-04-28

申请号：KR1020020063026

申请日：2002-10-16

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  박봉태

IPC: H01L27/115

Abstract: PURPOSE: An electrical connection line of a flash memory device and a manufacturing method thereof are provided to be capable of simply and easily forming a butting contact. CONSTITUTION: An electrical connection line of a flash memory device is provided with a semiconductor substrate, a plurality of lines formed on the semiconductor substrate, and a common source line(110) electrically connected to the semiconductor substrate between the lines. At this time, the line is completed by sequentially forming a gate dielectric layer(101), a floating gate(102), an interlayer dielectric(103), and a control gate(104,105). The electrical connection line further includes a butting contact(210) for electrically connecting the control gate with the floating gate and a bit line electrically connected to the common source line or the butting contact.

Abstract translation: 目的：提供闪存器件的电连接线及其制造方法，以便简单且容易地形成对接触点。 构成：闪速存储器件的电连接线设置有半导体衬底，形成在半导体衬底上的多条线，以及在线之间电连接到半导体衬底的公共源极线（110）。 此时，通过顺序地形成栅极电介质层（101），浮动栅极（102），层间电介质（103）和控制栅极（104,105）来完成线。 电连接线还包括用于将控制栅极与浮动栅极电连接的对接触点（210）和电连接到公共源极线或对接触点的位线。

公开(公告)号：KR1020060069030A

公开(公告)日：2006-06-21

申请号：KR1020040108020

申请日：2004-12-17

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  최승욱

IPC: H01L27/115

CPC classification number: H01L21/823425 ,  H01L21/76879

Abstract: 낸드형 비휘발성 메모리 소자의 형성 방법을 개시한다. 상기 방법에 따르면, 반도체 기판 상에 서로 평행한 스트링 선택 라인 및 접지 선택 라인, 그리고 상기 스트링 선택 라인 및 상기 접지 선택 라인 사이에 배치되는 복수개의 평행한 워드 라인들로 구비되는 스트링을 형성한다. 상기 반도체 기판 상에 층간절연막을 형성한다. 상기 층간절연막을 패터닝하여 상기 접지선택 라인과 이웃하는 접지선택 라인 사이의 상기 반도체 기판을 노출시키며 상기 접지선택 라인과 평행한 공통 소오스 라인 그루브를 형성하는 동시에 상기 스트링 선택 라인과 이웃하는 스트링 선택 라인 사이의 상기 반도체 기판을 노출시키는 비트라인 콘택홀을 형성한다. 도전막을 적층하여 상기 공통 소오스 라인 그루브 및 상기 비트라인 콘택홀을 채운다. 상기 도전막에 대해 평탄화 제거 공정을 진행하여 상기 층간절연막을 노출시키는 동시에 상기 공통 소오스 라인 그루브 안에 공통 소오스 라인을 형성하고 상기 비트라인 콘택홀 안에 비트라인 콘택플러그를 형성한다. 상기 공통 소오스 라인의 상부를 일부 제거한다. 그리고, 상기 공통 소오스 라인의 상부가 제거된 곳을 절연막으로 채운다.
낸드형 비휘발성 메모리 소자

公开(公告)号：KR100504689B1

公开(公告)日：2005-08-03

申请号：KR1020030000737

申请日：2003-01-07

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  박봉태

IPC: H01L27/115

Abstract: 본 발명은 비트 라인(BL)과 공통 소오스 라인(CSL)간의 절연효과가 높은 NAND형 플래시 메모리 소자 및 그의 제조방법을 개시한다. 개시된 본 발명은, 반도체 기판; 상기 기판상에 동일한 방향으로 신장되고 평행 배열된 스트링 선택 라인과 워드 라인과 접지 선택 라인을 포함하는 스트링; 상기 스트링을 이루는 각각의 라인이 신장되는 방향과 실질적으로 수직하는 방향으로 신장된 비트 라인; 상기 스트링 선택 라인의 드레인과 상기 비트 라인과는 전기적으로 도통되는 콘택 플러그; 및 상기 접지 선택 라인의 소오스와는 전기적으로 도통되는 하부막과, 상기 비트 라인과는 전기적으로 절연되는 상부막으로 구성되는 공통 소오스 라인을 포함하는 것을 특징으로 한다. 본 발명에 따르면, 비트 라인과 공통 소오스 라인 사이의 절연효과가 높아지는 효과가 있다. 또한, 절연막의 전체 높이를 낮아짐으로써 후속 공정이 용이해지는 효과가 있다.

公开(公告)号：KR1020030068776A

公开(公告)日：2003-08-25

申请号：KR1020020008389

申请日：2002-02-18

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  장원위 ,  박봉태

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

Abstract: PURPOSE: A non-volatile memory device is provided to reduce the resistance between a direct contact and a common source line and embody a stable driving by broadening a contact area between the direct contact and a bitline and a contact area between the common source line and the bitline. CONSTITUTION: The first insulation layer(112) is formed on a semiconductor substrate(110), including a direct contact pattern groove and a common source line pattern groove that penetrate into the semiconductor substrate. The direct contact(114) has such an extended area that the direct contact pattern groove and a protrusion extending to the upper portion of the direct contact pattern groove extend to the upper surface of the first insulation layer. The common source line(118) has such an extended area that the common source line pattern groove and a protrusion extending to the upper portion of the common source line pattern groove extend to the upper surface of the first insulation layer. The second insulation layer(124) is formed on the first insulation layer, including a plurality of bitline pattern grooves that expose the upper portions of the extended protrusions of the direct contact and the common source line. The bitline(126) is formed in the bitline pattern groove.

Abstract translation: 目的：提供一种非易失性存储器件，以减少直接接触和公共源极线之间的电阻，并通过扩大直接接触和位线之间的接触面积以及公共源极线与公共源极线之间的接触面积来实现稳定的驱动 位线。 构成：第一绝缘层（112）形成在半导体衬底（110）上，包括直接接触图案槽和穿入半导体衬底的公共源极线图案槽。 直接接触（114）具有这样的延伸区域：直接接触图形凹槽和延伸到直接接触图形凹槽的上部的突起延伸到第一绝缘层的上表面。 公共源极线（118）具有这样的扩展区域：公共源极线图形凹槽和延伸到公共源极线图案凹槽的上部的突起延伸到第一绝缘层的上表面。 第二绝缘层（124）形成在第一绝缘层上，包括暴露直接接触的延伸突起的上部和公共源极线的多个位线图案槽。 位线（126）形成在位线图形凹槽中。

公开(公告)号：KR1020040063350A

公开(公告)日：2004-07-14

申请号：KR1020030000737

申请日：2003-01-07

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  박봉태

IPC: H01L27/115

Abstract: PURPOSE: A NAND-type flash memory device is provided to improve an insulation effect between a bitline and a common source line, and to facilitate a subsequent process by decreasing the whole height of an insulation layer. CONSTITUTION: A semiconductor substrate(100) is prepared. A string(110) includes a string select line(300), a wordline(200) and a ground select line(400) that extend in the same direction on the substrate and are disposed in parallel. A bitline(700) extends in a direction substantially perpendicular to the extension direction of each line of the string. A contact plug is electrically connected to a drain(120) of the string select line and the bitline. A common source line(500) includes a lower layer(510) and an upper layer(520) wherein the lower layer is electrically connected to a source(140) of the ground select line and an upper layer is electrically insulated from the bitline.

Abstract translation: 目的：提供NAND型闪速存储器件以改善位线和公共源极线之间的绝缘效应，并且通过降低绝缘层的整个高度来促进随后的工艺。 构成：制备半导体衬底（100）。 串（110）包括串联选择线（300），字线（200）和接地选择线（400），其在基板上沿相同的方向延伸并且平行设置。 位线（700）在与弦线的每条线的延伸方向基本垂直的方向上延伸。 接触插塞电连接到串选择线和位线的漏极（120）。 公共源线（500）包括下层（510）和上层（520），其中下层电连接到地选线的源极（140），并且上层与位线电绝缘。

公开(公告)号：KR1020030073937A

公开(公告)日：2003-09-19

申请号：KR1020020013723

申请日：2002-03-14

Applicant: 삼성전자주식회사

Inventor： 박봉태 ,  조상연 ,  정연운

IPC: H01L21/8247

Abstract: PURPOSE: A method for fabricating a floating gate type non-volatile memory(NVM) device is provided to reduce an operating voltage by increasing the surface area of a floating gate electrode so that the capacitance of the floating gate electrode and a control gate electrode is increased. CONSTITUTION: An active region for forming an isolation layer(102) is defined in a predetermined region of a semiconductor substrate(101). A tunnel oxide layer(103) is formed on the active region. A floating gate pattern(104b) is formed on the tunnel oxide layer, having a cross section of a U type and exposing the isolation layer. A gate interlayer dielectric and a control gate layer are sequentially formed on the entire surface of the semiconductor substrate including the floating gate pattern. The control gate layer, the gate interlayer dielectric and the floating gate pattern are consecutively patterned to form the control gate electrode crossing the upper portion of the active region and the floating gate electrode interposed between the control gate electrode and the active region.

Abstract translation: 目的：提供一种用于制造浮动栅型非易失性存储器（NVM）器件的方法，通过增加浮栅电极的表面积来降低工作电压，使得浮栅电极和控制栅电极的电容为 增加。 构成：用于形成隔离层（102）的有源区限定在半导体衬底（101）的预定区域中。 隧道氧化物层（103）形成在有源区上。 在隧道氧化物层上形成浮栅图案（104b），其具有U型横截面并暴露隔离层。 在包括浮置栅极图案的半导体衬底的整个表面上依次形成栅极层间电介质和控制栅极层。 控制栅极层，栅极层间电介质和浮置栅极图案被连续地图案化以形成跨越有源区的上部的跨越控制栅电极和插在控制栅电极和有源区之间的浮栅。

公开(公告)号：KR1020020074551A

公开(公告)日：2002-10-04

申请号：KR1020010014324

申请日：2001-03-20

Applicant: 삼성전자주식회사

Inventor： 장원위 ,  이원홍 ,  은동석 ,  정연운

IPC: H01L21/28

Abstract: PURPOSE: A method for forming interconnection of a semiconductor device is provided to easily achieve stable contact resistance without misalignment in damascene processing. CONSTITUTION: A lower insulating layer(206), an etch stopper(208) and an upper insulating layer(210) are sequentially formed on a semiconductor substrate(200) having transistors. A groove is formed by selectively etching the upper insulating layer(210) to expose the etch stopper(208). The exposed etch stopper is then etched to expose the surface of the lower insulating layer(206). A contact hole is formed by selectively etching the exposed lower insulating layer. A bit line(222) is formed by filling a conductive material into the contact hole.

Abstract translation: 目的：提供一种用于形成半导体器件的互连的方法，以容易地实现稳定的接触电阻而不会在镶嵌处理中发生未对准。 构成：在具有晶体管的半导体衬底（200）上依次形成下绝缘层（206），蚀刻停止层（208）和上绝缘层（210）。 通过选择性地蚀刻上绝缘层（210）以暴露蚀刻停止件（208）形成凹槽。 然后蚀刻暴露的蚀刻停止层以暴露下绝缘层（206）的表面。 通过选择性地蚀刻暴露的下绝缘层形成接触孔。 通过将导电材料填充到接触孔中而形成位线（222）。

公开(公告)号：KR1020020013193A

公开(公告)日：2002-02-20

申请号：KR1020000046674

申请日：2000-08-11

Applicant: 삼성전자주식회사

Inventor： 장성남 ,  황덕성 ,  정연운 ,  박봉태

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/8247

Abstract: PURPOSE: A method for forming a common source line of a flash memory device is provided to easily form or fill a bit line contact hole and to reduce damage to an insulation between bit line contact plugs or a bit line and the common source line, by forming the common source line have the same height as the gate line. CONSTITUTION: A source line trench is formed in the common source line region in the course of forming an isolation trench on a silicon substrate(10). An ion implantation process is performed regarding the silicon substrate constituting the bottom surface of the source line trench. A floating gate layer(63',73) is stacked and patterned to form a floating gate string pattern, wherein the source line trench is filled in the floating gate layer to form the common source line.

Abstract translation: 目的：提供一种用于形成闪存器件的公共源极线的方法，以容易地形成或填充位线接触孔，并且通过以下方式减少对位线接触插塞或位线与公共源极线之间的绝缘的损坏，由 形成公共源极线具有与栅极线相同的高度。 构成：在硅衬底（10）上形成隔离沟槽的过程中，在公共源极线区域中形成源极线沟槽。 对构成源极线沟槽的底面的硅衬底进行离子注入工艺。 堆叠并图案化浮栅层（63'，73）以形成浮栅阵列图案，其中源极线沟槽填充在浮栅层中以形成公共源极线。

公开(公告)号：KR1020020075008A

公开(公告)日：2002-10-04

申请号：KR1020010015162

申请日：2001-03-23

Applicant: 삼성전자주식회사

Inventor： 정연운 ,  최정달 ,  장원위 ,  은동석

IPC: H01L21/762

Abstract: PURPOSE: A trench isolation structure and a method for forming the same are provided to improve a gap-filling property and to prevent an etch of an active region due to misalignment of a floating gate. CONSTITUTION: A floating gate oxide(202), a first floating gate(204) and a trench etch mask(206) are sequentially formed on a silicon substrate(200). A desired region of the silicon substrate(200) is exposed by sequentially patterning the trench etch mask, the first floating gate and the floating gate oxide. A trench(207) is formed by etching the exposed silicon substrate(200) using the trench etch mask pattern as a mask. At this time, the trench(207) is divided by a first trench sidewall(207a), a second trench sidewall(207a') and a trench bottom(207b). The first trench sidewall(207a) has nearly vertical sidewalls and the second trench sidewall(207a') has sloped sidewalls.

Abstract translation: 目的：提供一种沟槽隔离结构及其形成方法，以提高间隙填充性能，并防止浮动栅极的不对准导致的有源区域的蚀刻。 构造：在硅衬底（200）上依次形成浮栅氧化层（202），第一浮栅（204）和沟沟蚀刻掩模（206）。 通过对沟槽蚀刻掩模，第一浮动栅极和浮置栅极氧化物进行顺序图案化，曝光硅衬底（200）的期望区域。 通过使用沟槽蚀刻掩模图案作为掩模蚀刻暴露的硅衬底（200）来形成沟槽（207）。 此时，沟槽207被第一沟槽侧壁207a，第二沟槽侧壁207a，沟槽底部207b分隔。 第一沟槽侧壁（207a）具有几乎垂直的侧壁，第二沟槽侧壁（207a'）具有倾斜的侧壁。