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公开(公告)号：KR1020170065730A
公开(公告)日：2017-06-14
申请号：KR1020150171656
申请日：2015-12-03
Applicant: 삼성전자주식회사
IPC: H04N5/369
CPC classification number: H04N5/378 , H01L27/14605 , H01L27/14612 , H04N5/3456 , H04N5/3458 , H04N5/347 , H04N5/37457 , H04N9/045
Abstract: 본발명의실시예에따른이미지센서는열 방향으로순차적으로배열되는제 1 픽셀유닛내지제 4 픽셀유닛을포함하는액티브픽셀센서어레이를포함할수 있으며, 각각의픽셀유닛은복수의픽셀들로구성될수 있다. 제 1 픽셀유닛및 제 2 픽셀유닛을포함하는제 1 픽셀그룹은제 1 컬럼라인에연결되고, 제 3 픽셀유닛및 제 4 픽셀유닛을포함하는제 2 픽셀그룹은제 2 컬럼라인에연결될수 있다. 이미지센서는제 1 픽셀그룹중 선택된픽셀에의해감지된제 1 감지전압및 제 2 픽셀그룹중 선택된픽셀에의해감지된제 2 감지전압을상관이중샘플링신호들로변환하는제 1 상관이중샘플러및 제 2 상관이중샘플러를포함할수 있다. 제 1 감지전압과제 2 감지전압은제 1 상관이중샘플러와제 2 상관이중샘플러중 서로다른상관이중샘플러에의해상관이중샘플링신호들로각각변환될수 있다.
Abstract translation: 根据本发明的实施例的图像传感器可以是有源像素传感器阵列，其包括第一像素单元至所述第四像素单元被顺序排列在列方向上，每一个像素单元可以由多个像素的 有。 第一像素单元和包含像素单元的第二第一像素组被连接到第一列线，和包含像素单元和第四像素单元中的第三第二像素组可以连接到第二列线 。 图像传感器，包括：用于转换由所述第一感测电压的所选择的像素，并通过相关双采样信号的选择的像素和所检测的像素的第二组检测到的第二检测电压的像素的组的第一相关双采样器 2相关双采样器。 第一感测电压任务2检测电压可通过第一相关双采样器的不同的相关双采样器和第二相关双采样器被转换成各信号的相关双采样。
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公开(公告)号：KR1020160101294A
公开(公告)日：2016-08-25
申请号：KR1020150023351
申请日：2015-02-16
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11568 , H01L27/1157 , H01L27/11582 , H01L29/4234 , H01L29/42364 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/792 , H01L29/7923 , H01L27/11563 , H01L2924/1443
Abstract: 비휘발성메모리장치는기판상에적층된게이트전극들, 상기게이트전극들을관통하여상기기판에연결되는반도체패턴, 및상기반도체패턴과상기게이트전극들사이의전하저장층을포함한다. 상기전하저장층은상기반도체패턴과상기게이트전극들사이에개재되고제1 에너지밴드갭을갖는제1 전하저장층, 상기제1 전하저장층과상기반도체패턴사이에개재되고제2 에너지밴드갭을갖는제2 전하저장층, 및상기제1 전하저장층과상기게이트전극들사이에개재되고제3 에너지밴드갭을갖는제3 전하저장층을포함한다. 상기제1 에너지밴드갭은상기제2 및제3 에너지밴드갭들보다작다. 상기제1 전하저장층의두께는상기제2 및제3 전하저장층들의두께보다두껍다.
Abstract translation: 非易失性存储器件包括：堆叠在衬底上的栅极电极; 通过栅电极连接到衬底的半导体图案; 并且设置在半导体图案和栅电极之间的电荷存储层。 电荷存储层包括插入在半导体图案和栅电极之间并具有第一能带隙的第一电荷存储层; 插入在所述第一电荷存储层和所述半导体图案之间并具有第二能带隙的第二电荷存储层; 以及插入在所述第一电荷存储层和所述栅电极之间并具有第三能带隙的第三电荷存储层。 第一能带隙小于第二和第三能带隙。 第一电荷存储层的厚度大于第二和第三电荷存储层的厚度。
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公开(公告)号：KR1020160095281A
公开(公告)日：2016-08-11
申请号：KR1020150016169
申请日：2015-02-02
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11582 , H01L21/28282 , H01L27/11556 , H01L29/4234 , H01L29/42348 , H01L27/11521 , H01L2924/1443
Abstract: 본발명의반도체장치및 그의제조방법에관한것으로, 기판상에수직적으로적층된절연패턴들및 상기절연패턴들사이에게재된게이트패턴들을포함하는적층구조체, 상기적층구조체를관통하여상기기판과전기적으로연결되는활성기둥및 상기적층구조체와상기활성기둥사이에게재되는전하저장막을포함하되, 상기전하저장막은상기활성기둥과상기게이트패턴들사이의제1 영역들, 상기활성기둥과상기절연패턴들사이의제2 영역들및 상기제1 영역들과상기제2 영역들을연결하는제3 영역들을포함하되, 상기제3 영역들은, 라운드진형상의내측벽을가지며상기제1 영역들보다얇은두께를갖는부분을포함하는반도체장치가제공된다.
Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括：层压结构，其包括垂直层叠在基板上的叠层图案，以及介于绝缘图案之间的栅极图案; 活性柱，其穿透层叠结构，并且电连接到基板; 以及介于层叠结构和活性柱之间的电荷存储膜。 电荷存储膜包括：位于有源列和栅极图案之间的第一区域; 位于活性柱和绝缘图案之间的第二区域; 以及连接第一区域和第二区域的第三区域。 第三区域包括圆形内侧和厚度比第一区域薄的部分。
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公开(公告)号：KR1020140111853A
公开(公告)日：2014-09-22
申请号：KR1020130026291
申请日：2013-03-12
Applicant: 삼성전자주식회사
CPC classification number: H04N5/3575 , H04N5/37457 , H04N5/378 , H04N9/045
Abstract: The present invention relates to a method for simultaneously reading out two rows of an image sensor. In the odd-numbered horizontal period, a photoelectric charge of a first color of one photoelectric conversion element which shares a read circuit of unit pixel areas is read out in a first column line through the read circuit, and a photoelectric charge of a second color of another photoelectric conversion element of an unit pixel area adjacent in the column direction is read out in a second column line through the read circuit of the adjacent unit pixel area. In the even-numbered horizontal period, a photoelectric charge of a second color of another photoelectric conversion element of a unit pixel area is read out to the second column line through the read circuit, and a photoelectric charge of a first color of one photoelectric conversion element of an adjacent unit pixel area is read out to the first column line through an adjacent read circuit. Therefore, mismatches can be prevented by reading out the same color through the same column line when simultaneously reading out two rows.
Abstract translation: 本发明涉及一种用于同时读出两行图像传感器的方法。 在奇数水平周期中，通过读取电路在第一列线中读出共享单位像素区域的读取电路的一个光电转换元件的第一颜色的光电荷，并且将第二颜色的光电荷 通过相邻单位像素区域的读取电路在第二列线中读出在列方向上相邻的单位像素区域的另一个光电转换元件。 在偶数水平周期中，通过读取电路将单位像素区域的另一光电转换元件的第二颜色的光电荷读出到第二列线，并且将一个光电转换的第一颜色的光电荷 通过相邻的读取电路将相邻单位像素区域的元素读出到第一列线。 因此，当同时读出两行时，可以通过同一列线读出相同的颜色来防止错配。
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Patent Agency Ranking
公开(公告)号：KR1020140067408A
公开(公告)日：2014-06-05
申请号：KR1020120134595
申请日：2012-11-26
Applicant: 삼성전자주식회사
IPC: H04N5/361
Abstract: A solid image pick-up device having a dark offset compensation circuit is disclosed. The solid image pick-up device comprises: a pixel array; an A/D conversion unit for converting a pixel signal corresponding to charges accumulated to a photoelectric conversion element into a digital signal; a ramp signal generator for generating a ramp signal in response to a control signal to be used for A/D conversion; and a dark offset compensation circuit for compensating dark offset by using a gain setting value and dark offset to perform processing of an input signal only in a full range of an input signal level by being connected to the A/D conversion unit and the ramp signal generator. Thereby, burden on the circuit can be reduced while the dark offset compensation is performed more efficiently.
Abstract translation: 公开了一种具有暗偏移补偿电路的固体摄像装置。 固体摄像装置包括：像素阵列; A / D转换单元，用于将对应于累积到光电转换元件的电荷的像素信号转换成数字信号; 斜坡信号发生器，用于响应于要用于A / D转换的控制信号而产生斜坡信号; 以及暗偏移补偿电路，用于通过使用增益设定值和暗偏移来补偿暗偏移，仅通过连接到A / D转换单元和斜波信号来在输入信号电平的全范围内执行输入信号的处理 发电机。 由此，能够更有效地进行暗偏移补偿，能够减轻电路的负担。
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公开(公告)号：KR1020120048997A
公开(公告)日：2012-05-16
申请号：KR1020100110533
申请日：2010-11-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7926 , H01L21/76205 , H01L27/0688
Abstract: PURPOSE: A three dimensional semiconductor memory device is provided to prevent impurities for controlling a threshold voltage from being diffused by forming a diffusion prevention impurity region in an active pattern. CONSTITUTION: Conductive patterns(230) and insulating layers(121-128) are formed on a substrate(10). A first structure(VS) is formed in a channel hole(105) passing through the conductive patterns. The first structure includes an active pattern(173) and a first buried pattern(181). An information storage film(220) is formed between the conductive patterns and the first structures. A second impurity region(155) is formed on the top of the first structures.
Abstract translation: 目的：提供三维半导体存储器件，以通过形成活性图案中的防扩散杂质区域来防止杂质控制阈值电压的扩散。 构成：在基板（10）上形成导电图案（230）和绝缘层（121-128）。 第一结构（VS）形成在通过导电图案的通道孔（105）中。 第一结构包括有源图案（173）和第一掩埋图案（181）。 在导电图案和第一结构之间形成信息存储膜（220）。 在第一结构的顶部上形成第二杂质区（155）。
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公开(公告)号：KR100843229B1
公开(公告)日：2008-07-02
申请号：KR1020070003395
申请日：2007-01-11
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7881 , H01L29/792 , B82Y10/00
Abstract: A flash memory device including a charge trap layer of a hybrid structure and a method for manufacturing the same are provided to enhance retention characteristics of electric charges by capturing electrons at a low energy level. A tunneling insulating layer(120) is formed on a semiconductor substrate. A charge trap layer(130) is formed on the tunneling insulating layer. A blocking insulating layer(160) is formed on the charge trap layer. A control gate electrode is formed on the blocking insulating layer. The charge trap layer includes a first trap layer formed with a first material having a first band gap energy level, and at least one hybrid trap layer(132,134) having a plurality of nano-dots. The nano-dots are partially surrounded by the first trap layer. The nano-dots are separated in a predetermined interval from each other. The nano-dots are composed of a second material having low band gap energy. Each of the nano-dots has a nitrated surface.
Abstract translation: 提供了包括混合结构的电荷陷阱层的闪存器件及其制造方法，以通过在低能级捕获电子来增强电荷的保持特性。 隧道绝缘层（120）形成在半导体衬底上。 在隧道绝缘层上形成电荷陷阱层（130）。 在电荷陷阱层上形成阻挡绝缘层（160）。 控制栅电极形成在阻挡绝缘层上。 电荷陷阱层包括形成有具有第一带隙能级的第一材料的第一陷阱层和具有多个纳米点的至少一个混合陷阱层（132,134）。 纳米点被第一陷阱层部分地包围。 纳米点以预定间隔彼此分离。 纳米点由具有低带隙能量的第二材料组成。 每个纳米点都具有硝化表面。
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公开(公告)号：KR1020080046484A
公开(公告)日：2008-05-27
申请号：KR1020060116006
申请日：2006-11-22
Applicant: 삼성전자주식회사
IPC: H03M1/12
CPC classification number: H03M1/1019 , H03M1/1023 , H03M1/1071 , H03M2201/639 , H03M2201/64 , H03M2201/65
Abstract: An analog-to-digital conversion method is provided to secure a correct analog-to-digital conversion process by modifying upper bits wrongly outputted by parasitic capacitors, a finite voltage gain, noise by a temperature, and a feed-through. An analog-to-digital conversion method includes the steps of: generating a lamp signal corresponding to digital data while changing an upper (N-K) bit of the digital data(S02); comparing a sensed image signal with the lamp signal(S03); determining a value of the upper (N-K) bit of the digital data according to a comparison of the lamp signal and the sensed image signal(S04); generating the lamp signal corresponding to the digital data while changing a lower (K+1) bit of the digital data(S05); comparing a voltage level of the sensed image signal with the sum of the lamp signal and a compensation value(S06); determining a value of a lower K bit of the digital data when the sum of the lamp signal and the compensation value is equal to the voltage level of the sensed image signal(S07); and adjusting the value of the upper (N-K) bit of the digital data according to a most significant 2-bit value of the lower (K+1) bit(S08).
Abstract translation: 提供了一种模数转换方法，用于通过修改由寄生电容器错误输出的高位，有限电压增益，噪声，温度和馈通来确保正确的模数转换过程。 一种模数转换方法包括以下步骤：在改变数字数据的上（N-K）位的同时产生对应于数字数据的灯信号（S02）; 将感测到的图像信号与灯信号进行比较（S03）; 根据灯信号和感测图像信号的比较，确定数字数据的上（N-K）位的值（S04）; 在改变数字数据的较低（K + 1）位的同时，产生与数字数据对应的灯信号（S05）; 将感测图像信号的电压电平与灯信号和补偿值的和进行比较（S06）; 当灯信号和补偿值的总和等于感测图像信号的电压电平时，确定数字数据的较低K位的值（S07）; 并根据较低（K + 1）比特的最高有效2比特值调整数字数据的上（N-K）比特的值（S08）。
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