公开(公告)号：KR1020130075158A

公开(公告)日：2013-07-05

申请号：KR1020110143409

申请日：2011-12-27

Applicant: 삼성전자주식회사

Inventor： 조한나 ,  이동석 ,  홍정표

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/04 ,  H01L21/31144 ,  H01L21/32137 ,  H01L27/11582 ,  H01L28/90 ,  H01L29/66545 ,  H01L29/66825 ,  H01L21/76205

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to easily remove a carbon film which remains after an etching object film is etched by forming the carbon film with different boron concentration. CONSTITUTION: An etching object film (115) is formed on a substrate (100). A carbon film (120) doped with boron is formed on the etching object film. The boron concentration of the upper side of the carbon film is different from the boron concentration of the lower side of the carbon film. At least one opening part is formed to expose the etching object film by patterning the carbon film. The exposed etching object film is etched by using the carbon film as an etching mask.

Abstract translation: 目的：提供一种制造半导体器件的方法，以便通过形成具有不同硼浓度的碳膜来容易地除去蚀刻对象膜后留下的碳膜。 构成：在基板（100）上形成蚀刻对象膜（115）。 在蚀刻对象膜上形成掺杂有硼的碳膜（120）。 碳膜的上侧的硼浓度与碳膜的下侧的硼浓度不同。 形成至少一个开口部分，以通过图案化碳膜来暴露蚀刻对象膜。 通过使用碳膜作为蚀刻掩模蚀刻暴露的蚀刻对象膜。

公开(公告)号：KR1020140027666A

公开(公告)日：2014-03-07

申请号：KR1020120093498

申请日：2012-08-27

Applicant: 삼성전자주식회사

Inventor： 오정익 ,  장대현 ,  이성수 ,  조한나

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/308 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76885 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/28282

Abstract: A method for forming stair-typed patterns forms a laminating structure by repeatedly laminating an interlayer insulating film and a sacrificial film on a substrate. An n^th preliminary stair pattern is formed using a first photo resist pattern formed on the laminating structure as an etching mask and etching the interlayer insulating film and the sacrificial film of the top of the first floor. A first inorganic protective film pattern to cover the top of the first photo resist pattern is formed. A second photo resist pattern is formed by partially removing the lateral side of the first photo resist pattern. An (n+1)^th preliminary stair pattern is formed using the second photo resist pattern and each etching the interlayer insulating film and the sacrificial film of the top of the first floor, an interlayer insulating film and a sacrificial film of the first floor under the top exposed in the n^th preliminary stair pattern. Furthermore, the target number of stair patterns is formed by repeatedly performing from a process for forming a first protective pattern and to a process to form the n+1 preliminary stair pattern relative to the n+1 preliminary stair pattern.

Abstract translation: 用于形成楼梯型图案的方法通过在基板上反复层压层间绝缘膜和牺牲膜而形成层压结构。 使用形成在层压结构上的第一光致抗蚀剂图案作为蚀刻掩模形成第n个初步阶梯图案，并蚀刻层间绝缘膜和第一层顶部的牺牲膜。 形成覆盖第一光致抗蚀剂图案的顶部的第一无机保护膜图案。 通过部分去除第一光致抗蚀剂图案的侧面来形成第二光致抗蚀剂图案。 使用第二光致抗蚀剂图案形成第（n + 1）个初步阶梯图案，并且分别蚀刻层间绝缘膜和第一层顶部的牺牲膜，第一层的层间绝缘膜和牺牲膜 在顶部暴露在第n个初步阶梯模式。 此外，通过从用于形成第一保护图案的处理重复执行并且相对于n + 1初步阶梯图案形成n + 1初步阶梯图案的处理来形成楼梯图案的目标数量。

公开(公告)号：KR1020170036479A

公开(公告)日：2017-04-03

申请号：KR1020150135697

申请日：2015-09-24

Applicant: 삼성전자주식회사

Inventor： 조한나 ,  김종규 ,  김혁 ,  박종철

IPC: H01L21/3065 ,  H01L21/02

CPC classification number: H01J37/32009 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01J37/3266 ,  H01J37/32669 ,  H01J37/32715

Abstract: 이온빔 에칭장치에관한것이다. 이이온빔 에칭장치는이온빔의진행경로에가변자기장을인가할수 있다. 이온소스일측에그리드가형성될수 있으며, 그리드는이온을가속시켜이온빔을방사또는발사한다. 공정챔버에서는이온빔을이용한에칭공정등의공정이수행되며, 가변자기장인가부는공정챔버주변에형성되어가변자기장을인가할수 있다.

Abstract translation: 用于离子束蚀刻设备。 离子束蚀刻设备可以将可变磁场施加到离子束的路径。 栅格可以形成在离子源的一侧，栅格加速离子发射或发射离子束。 在处理室中，执行诸如使用离子束的蚀刻处理之类的处理，并且在处理室周围形成可变磁场施加单元以施加可变磁场。

公开(公告)号：KR1020080026759A

公开(公告)日：2008-03-26

申请号：KR1020060091732

申请日：2006-09-21

Applicant: 삼성전자주식회사

Inventor： 최윤석 ,  장영진 ,  최재범 ,  심승환 ,  조한나

IPC: G02F1/1335

CPC classification number: G02F1/1368 ,  G02F1/133553 ,  G02F1/136227 ,  H01L29/78618

Abstract: A TFT(Thin Film Transistor) substrate, a method for manufacturing the same, and a display device having the same are provided to improve optical reflexibility by forming a non-reflective film on a metallic layer to form source and drain electrodes, preventing the reflection of light due to the metallic layer when an organic protection film is uniformly exposed, and forming a uniform uneven pattern. A TFT substrate(100) comprises a substrate, gate electrodes(111), source electrodes(131), drain electrodes(132), a non-reflective film(150), an organic protection film(160), pixel electrodes(170), and a reflective film(180). The gate electrodes are formed on the substrate. The source and drain electrodes are arranged above the gate electrodes. The non-reflective film is laid on the source and drain electrodes. The organic protection film, formed at the front of the substrate which contains the non-reflective film, has an uneven pattern. The pixel electrodes and the reflective film are patterned on the organic protection film.

Abstract translation: 提供TFT（薄膜晶体管）基板及其制造方法以及具有该TFT的薄膜晶体管的显示装置，以通过在金属层上形成非反射膜来形成源极和漏极，从而提高光学反射性，从而防止反射 当有机保护膜均匀地暴露时由于金属层而产生的光，并且形成均匀的不均匀图案。 TFT基板（100）包括基板，栅极（111），源电极（131），漏电极（132），非反射膜（150），有机保护膜（160），像素电极（170） ，和反射膜（180）。 栅电极形成在基板上。 源电极和漏极布置在栅电极上方。 非反射膜放置在源极和漏极上。 在包含非反射膜的基板的前部形成的有机保护膜具有不均匀的图案。 像素电极和反射膜在有机保护膜上图案化。

公开(公告)号：KR1020080026758A

公开(公告)日：2008-03-26

申请号：KR1020060091731

申请日：2006-09-21

Applicant: 삼성전자주식회사

Inventor： 최윤석 ,  장영진 ,  최재범 ,  심승환 ,  조한나

IPC: H01L29/786

CPC classification number: H01L27/1248 ,  G02F1/136227 ,  H01L27/1288

Abstract: A method for manufacturing a substrate for a thin film transistor is provided to simplify a manufacturing process by forming a recessed pattern and a drain contact hole on an organic capping layer through performing an exposure and developing processes once. A thin film transistor(130) is formed on a substrate(100), and then a passivation layer(140) and an organic capping layer(150) are formed on the substrate. A groove for contact hole and a recessed pattern(153) having a depth shallower than that of the groove are formed on the organic capping layer. A bottom surface of the groove and the passivation layer under the bottom surface are removed to form a drain contact hole(162) for exposing a portion of a drain electrode(132) of the thin film transistor. A pixel electrode(170) and a reflective layer(180) are formed on the organic capping layer.

Abstract translation: 提供一种用于制造薄膜晶体管的基板的方法，以通过一次进行曝光和显影处理，在有机覆盖层上形成凹陷图案和漏极接触孔来简化制造过程。 在衬底（100）上形成薄膜晶体管（130），然后在衬底上形成钝化层（140）和有机覆盖层（150）。 在有机覆盖层上形成有用于接触孔的凹槽和具有比凹槽深的深度的凹陷图案（153）。 除去槽的底表面和底表面下方的钝化层，以形成用于暴露薄膜晶体管的漏电极（132）的一部分的漏极接触孔（162）。 在有机覆盖层上形成像素电极（170）和反射层（180）。

公开(公告)号：KR1020080015666A

公开(公告)日：2008-02-20

申请号：KR1020060077295

申请日：2006-08-16

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 최재범 ,  장영진 ,  최윤석 ,  심승환 ,  조한나 ,  신중훈 ,  고준영

IPC: G02F1/136

CPC classification number: H01L21/02672 ,  H01L21/02532 ,  H01L27/1277 ,  H01L27/1281

Abstract: A method for manufacturing a thin film transistor substrate is provided to crystallize an amorphous silicon film with a minimum ion amount required for crystallizing to minimize the amount of nickel contained in the crystallized silicon layer by using a sacrificial layer, thereby improving the quality of the thin film transistor substrate. An amorphous silicon film is formed on an insulating substrate(110). A sacrificial film having an embossed surface is formed on the amorphous silicon film. The amorphous silicon film is crystallized into a polycrystalline silicon layer by contacting a metal plate with the sacrificial film and performing thermal treatment on the amorphous silicon film. The metal plate and the sacrificial film are removed. The polycrystalline silicon film is pattern-etched to form a semiconductor pattern(151). A gate insulating layer(140) is formed to cover the semiconductor pattern. A gate line is formed on the gate insulating layer, wherein a portion of the gate line overlaps the semiconductor pattern. Source and drain regions(153,155) are formed by heavily doping conductive impurities into portions of the semiconductor pattern. An interlayer insulating layer is formed to cover the gate line and the semiconductor pattern. A data line(171) and an output electrode(175) respectively connected to the source and drain regions are formed on the interlayer insulating layer.

Abstract translation: 提供一种制造薄膜晶体管基板的方法，以结晶所需的最小离子量使非晶硅膜结晶，以通过使用牺牲层将结晶硅层中所含的镍的量最小化，从而提高薄膜晶体管的质量 薄膜晶体管衬底。 在绝缘基板（110）上形成非晶硅膜。 在非晶硅膜上形成具有压花表面的牺牲膜。 通过使金属板与牺牲膜接触并对非晶硅膜进行热处理，将非晶硅膜结晶成多晶硅层。 去除金属板和牺牲膜。 对多晶硅膜进行图案蚀刻以形成半导体图案（151）。 形成栅极绝缘层（140）以覆盖半导体图案。 栅极线形成在栅极绝缘层上，其中栅极线的一部分与半导体图案重叠。 源极和漏极区（153,155）通过将导电杂质重掺杂到半导体图案的部分中而形成。 形成层间绝缘层以覆盖栅极线和半导体图案。 分别连接到源区和漏区的数据线（171）和输出电极（175）形成在层间绝缘层上。

公开(公告)号：KR101881857B1

公开(公告)日：2018-08-24

申请号：KR1020120093498

申请日：2012-08-27

Applicant: 삼성전자주식회사

Inventor： 오정익 ,  장대현 ,  이성수 ,  조한나

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/308 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76885 ,  H01L27/11575 ,  H01L27/11582

Abstract: 계단형패턴형성방법으로, 기판상에층간절연막및 희생막을반복적층하여적층구조물을형성한다. 상기적층구조물상에형성된제1 포토레지스트패턴을식각마스크로사용하여최상부 1층의층간절연막및 희생막을식각하여제n 예비계단패턴을형성한다. 상기제1 포토레지스트패턴의상부면을덮는무기물의제1 보호막패턴을형성한다. 상기제1 포토레지스트패턴의측벽부위를일부제거하여제2 포토레지스트패턴을형성한다. 상기제2 포토레지스트패턴을식각마스크로사용하여최상부 1층의층간절연막및 희생막과, 상기제n 예비계단패턴에서노출된상부면아래의 1층의층간절연막및 희생막을각각식각하여제n+1 예비계단패턴을형성한다. 또한, 상기제n+1 예비계단패턴에대해, 상기제1 보호막패턴을형성하는공정에서부터상기제n+1 예비계단패턴을형성하는공정까지를반복하여수행함으로써, 목표한층수의계단패턴을형성한다.