公开(公告)号：KR101675319B1

公开(公告)日：2016-11-14

申请号：KR1020100096470

申请日：2010-10-04

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  박문한 ,  김은곤 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/517 ,  H01L29/518

Abstract: 반도체소자의제조방법에서, 기판상에고유전물질을포함하는게이트절연막을형성한다. 게이트절연막상에식각저지막을형성한다. 식각저지막상에금속막을형성한다. 금속막상에비정질실리콘을포함하는하드마스크를형성한다. 하드마스크를식각마스크로사용하여금속막을패터닝함으로써금속막패턴을형성한다. 상기반도체소자의제조방법에서하드마스크와식각저지막을사용함으로써게이트절연막을보호하고게이트패터닝정밀도를향상시킬수 있다.

公开(公告)号：KR101666403B1

公开(公告)日：2016-10-17

申请号：KR1020100054420

申请日：2010-06-09

Applicant: 삼성전자주식회사

Inventor： 도진호 ,  임하진 ,  김원홍 ,  정회성 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/51 ,  H01L29/513

Abstract: 반도체소자의제조방법이제공된다. 본발명의일 실시예에따른반도체소자의제조방법은, 반도체기판상에에피택셜(epitaxial)층을성장시키는단계와, 상기에피택셜층상에제1 두께를갖는캡핑(capping)층을형성하는단계와, 상기캡핑층을산소분위기에서산화시켜제2 두께를갖는제1 게이트절연막을형성하는단계를포함한다.

公开(公告)号：KR1020120054935A

公开(公告)日：2012-05-31

申请号：KR1020100116338

申请日：2010-11-22

Applicant: 삼성전자주식회사

Inventor： 김원홍 ,  주대권

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/31

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: PURPOSE: A semiconductor device which utilizes a high dielectric layer as a gate insulating layer and a manufacturing method thereof are provided to minimize wet etch rate of an upper gate insulating film by forming the upper gate insulating film with nitrogen density lower than the nitrogen density of a lower gate insulating film. CONSTITUTION: A nitrogen-included lower gate insulating film is formed on a semiconductor substrate(1). An upper gate insulating film(11) is formed on the nitrogen-included lower gate insulating film. A lower metal film(18) is formed on the upper gate insulating film. The lower metal film within a first region is selectively removed. A lower metal film pattern remaining within a second region is formed.

Abstract translation: 目的：提供一种利用高电介质层作为栅极绝缘层的半导体器件及其制造方法，以通过形成具有低于氮绝缘膜的氮密度的上限栅极绝缘膜来最小化上部栅极绝缘膜的湿蚀刻速率 下栅绝缘膜。 构成：在半导体衬底（1）上形成含氮的下部栅极绝缘膜。 在含氮的下栅极绝缘膜上形成上部栅极绝缘膜（11）。 在上栅极绝缘膜上形成下金属膜（18）。 选择性地去除第一区域内的下部金属膜。 形成保留在第二区域内的下部金属膜图案。

公开(公告)号：KR1020120030710A

公开(公告)日：2012-03-29

申请号：KR1020100092394

申请日：2010-09-20

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  박문한 ,  송민우 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/10873 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L27/10814 ,  H01L27/10894 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/42324

Abstract: PURPOSE: A gate structure, a forming method thereof, and a method for manufacturing a semiconductor device including the same are provided to prevent an interface oxide film from being formed between a metal film and an amorphous silicon film by forming the amorphous silicon film on the metal film. CONSTITUTION: A gate insulating film including a high dielectric material is formed on a substrate(100). A metal film is formed on the gate insulating film. A PVD(Physical Vapor Deposition) process is performed and an amorphous silicon film is formed on a metal film. A polysilicon film on which impurity is doped is formed on the amorphous silicon film. The impurity is activated by performing an annealing process on a substrate.

Abstract translation: 目的：提供一种栅极结构及其形成方法及其制造方法，用于通过在非晶硅膜上形成非晶硅膜来防止在金属膜和非晶硅膜之间形成界面氧化膜 金属膜。 构成：在基板（100）上形成包括高电介质材料的栅极绝缘膜。 在栅极绝缘膜上形成金属膜。 进行PVD（物理气相沉积）工艺，并在金属膜上形成非晶硅膜。 在非晶硅膜上形成掺杂有杂质的多晶硅膜。 通过在衬底上进行退火处理来激活杂质。

公开(公告)号：KR1020120035017A

公开(公告)日：2012-04-13

申请号：KR1020100096470

申请日：2010-10-04

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  박문한 ,  김은곤 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to protect a gate insulation layer by using a hard mask and an etch stop layer. CONSTITUTION: A gate insulation layer(120) including high dielectric materials is formed on a substrate. An etch stop layer(130) is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask(155) including amorphous silicon is formed on the metal layer. A metal film pattern(142) is formed by patterning the metal layer using the hard mask as an etch mask.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过使用硬掩模和蚀刻停止层来保护栅极绝缘层。 构成：在基板上形成包括高介电材料的栅绝缘层（120）。 在栅极绝缘层上形成蚀刻停止层（130）。 在蚀刻停止层上形成金属层。 在金属层上形成包括非晶硅的硬掩模（155）。 通过使用硬掩模作为蚀刻掩模对金属层进行图案化来形成金属膜图案（142）。

公开(公告)号：KR1020110134696A

公开(公告)日：2011-12-15

申请号：KR1020100054420

申请日：2010-06-09

Applicant: 삼성전자주식회사

Inventor： 도진호 ,  임하진 ,  김원홍 ,  정회성 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/51 ,  H01L29/513 ,  H01L29/4232

Abstract: PURPOSE: A fabricating method of a semiconductor device is provided to improve the reliability of a whole semiconductor device by forming a first gate insulating film having improved a TDDB(Time Dependent Dielectric Breakdown) property. CONSTITUTION: In a fabricating method of a semiconductor device, an epitaxial layer is grown up on a semiconductor substrate(S1010). A capping layer is formed on the epitaxial layer(S1020). A first gate insulating layer is formed by oxidizing the capping layer under oxygen. A second gate insulating layer is formed in the first gate insulating film(S1040).

Abstract translation: 目的：提供半导体器件的制造方法，以通过形成具有改进的TDDB（时间依赖介电击穿）特性的第一栅极绝缘膜来提高整个半导体器件的可靠性。 构成：在半导体器件的制造方法中，在半导体衬底上生长外延层（S1010）。 在外延层上形成覆盖层（S1020）。 通过在氧气下氧化封盖层形成第一栅极绝缘层。 在第一栅极绝缘膜中形成第二栅极绝缘层（S1040）。

公开(公告)号：KR101674398B1

公开(公告)日：2016-11-10

申请号：KR1020100074878

申请日：2010-08-03

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4966

Abstract: 반도체소자의제조방법에서, 제1 영역및 제2 영역을갖는기판상에고유전물질을포함하는게이트절연막을형성한다. 제2 영역상의게이트절연막부분상에제1 금속을포함하는확산방지막을형성한다. 게이트절연막및 확산방지막상에확산막을형성한다. 기판을열처리하여확산막의성분을제1 영역상의게이트절연막부분으로확산시킨다. 확산막의잔류부분을제거한다. 게이트절연막및 확산방지막상에제2 금속을포함하는게이트전극막을형성한다. 상기반도체소자는금속을포함하는확산방지막을 PMOS 영역에만형성하므로, 우수한동작특성을갖는다.

公开(公告)号：KR1020110084733A

公开(公告)日：2011-07-26

申请号：KR1020100004447

申请日：2010-01-18

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  김명선 ,  정회성 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

Abstract: PURPOSE: Semiconductor devices with MOS transistors which optimized channel regions and manufacturing methods thereof are provided to form an upper semiconductor pattern by a silicon film and form a lower semiconductor pattern by a silicon-germanium film, thereby reducing the threshold voltage of a PMOS transistor. CONSTITUTION: A semiconductor device is formed on a fixed area of a semiconductor substrate and includes a device separation film(14) which defines an active area. The active area includes an inclined edge surface(9e). A semiconductor epitaxial pattern is covered on the upper center and the edge of the active area. A gate pattern crosses the upper part of the semiconductor epitaxial pattern.

Abstract translation: 目的：提供具有优化沟道区域的MOS晶体管的半导体器件及其制造方法，以通过硅膜形成上半导体图案，并通过硅 - 锗膜形成下半导体图案，从而降低PMOS晶体管的阈值电压。 构成：半导体器件形成在半导体衬底的固定区域上，并且包括限定有源区的器件分离膜（14）。 有源区域包括倾斜边缘表面（9e）。 半导体外延图案被覆盖在有效区域的上中心和边缘上。 栅极图案与半导体外延图案的上部相交。

公开(公告)号：KR101576203B1

公开(公告)日：2015-12-11

申请号：KR1020100004447

申请日：2010-01-18

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  김명선 ,  정회성 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

Abstract: 모스트랜지스터들을구비하는반도체소자가제공된다. 상기반도체소자는반도체기판의소정영역에형성되어활성영역을한정하는소자분리막을구비한다. 상기활성영역은 (100) 결정면(crystal plane)의중심상면(central top surface) 및상기중심상면으로부터상기소자분리막을향하여연장하는경사진가장자리표면(inclined edge surface)을갖는다. 상기활성영역의상기중심상면및 상기가장자리표면은반도체에피택시얼패턴으로덮여진다. 상기반도체에피택시얼패턴은상기중심상면에평행한 (100) 결정면의평평한상면및 상기평평한상면에실질적으로수직한(perpendicular) 측벽을구비한다. 상기반도체에피택시얼패턴의상부를가로지르도록게이트패턴이배치된다. 상기반도체소자의제조방법들또한제공된다.

公开(公告)号：KR1020120012705A

公开(公告)日：2012-02-10

申请号：KR1020100074878

申请日：2010-08-03

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4966

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to eliminate a remaining part of a diffusion film, thereby improving working speed of a transistor. CONSTITUTION: A gate insulating film including high dielectric materials is arranged on a substrate(100) which includes a first region(I) and a second region(II). A diffusion barrier film including a first metal is arranged on the second region of the gate insulating film. A diffusion film is arranged on the gate insulating film and the diffusion barrier film. The components of the diffusion film are diffused to the first region of the gate insulating film. A remaining portion of the diffusion film is removed. A gate electrode film which includes a second metal is arranged on the diffusion barrier film and the gate insulating film.

Abstract translation: 目的：提供半导体器件及其制造方法以消除扩散膜的剩余部分，从而提高晶体管的工作速度。 构成：包括高介电材料的栅极绝缘膜布置在包括第一区域（I）和第二区域（II）的基板（100）上。 包括第一金属的扩散阻挡膜布置在栅极绝缘膜的第二区域上。 扩散膜设置在栅极绝缘膜和扩散阻挡膜上。 扩散膜的成分扩散到栅极绝缘膜的第一区域。 去除扩散膜的剩余部分。 包括第二金属的栅极电极膜设置在扩散阻挡膜和栅极绝缘膜上。