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公开(公告)号：KR1020060123808A
公开(公告)日：2006-12-05
申请号：KR1020050045385
申请日：2005-05-30
Applicant: 삼성전자주식회사
IPC: H01L21/8242
CPC classification number: H01L21/31138 , B08B7/00 , B08B7/0035 , G03F7/427 , H01L28/91
Abstract: A method for removing photoresist is provided to cleanly remove the photoresist remaining in an opening with an aspect ratio by using ozone vapor not including water. A part of the photoresist is removed by an ashing process using plasma(S220). Ozone air is supplied to the surface of a substrate on which photoresist remains(S230). The photoresist remaining on the substrate is oxidized and analyzed by using the ozone vapor so as to be eliminated(S240). A rinse process using water is performed to eliminate the oxidized and analyzed photoresist from the substrate(S250).
Abstract translation: 提供了去除光致抗蚀剂的方法，通过使用不包括水的臭氧蒸气，以宽高比干净地去除残留在开口中的光致抗蚀剂。 通过使用等离子体的灰化处理去除部分光致抗蚀剂（S220）。 臭氧空气被供应到残留有光致抗蚀剂的基板的表面（S230）。 残留在基板上的光致抗蚀剂被氧化并通过使用臭氧蒸汽进行分析以被去除（S240）。 进行使用水的冲洗处理以从衬底去除氧化和分析的光致抗蚀剂（S250）。
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公开(公告)号：KR1020120111375A
公开(公告)日：2012-10-10
申请号：KR1020110029808
申请日：2011-03-31
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11578 , H01L21/823487 , H01L27/0688 , H01L27/11582 , H01L29/7926
Abstract: PURPOSE: A 3D semiconductor memory device and a manufacturing method thereof are provided to minimize the etch loss of the top electrode by covering a first outside will of the top electrode using an extension unit of an electrode-dielectric film. CONSTITUTION: An electrode structure includes electrodes(GSE1,GSE2,CE,SSE2,SSE1) and insulating patterns(505a,505nUa,505Ua). The electrodes are repetitively laminated on a substrate(100). The top electrode among the electrodes has a first outside wall and a second outside wall facing each other. A vertical active pattern(520) passes through the electrode structure. An electrode-dielectric film(570) is interposed between a sidewall of the vertical active pattern and each electrode.
Abstract translation: 目的：提供一种3D半导体存储器件及其制造方法，以通过使用电极 - 电介质膜的延伸单元覆盖顶部电极的第一外部部分来最小化顶部电极的蚀刻损耗。 构成：电极结构包括电极（GSE1，GSE2，CE，SSE2，SSE1）和绝缘图案（505a，505nUa，505Ua）。 电极重复层叠在基板（100）上。 电极中的顶部电极具有彼此面对的第一外壁和第二外壁。 垂直有源图案（520）穿过电极结构。 电极 - 电介质膜（570）插入在垂直有源图案的侧壁和每个电极之间。
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公开(公告)号：KR100666380B1
公开(公告)日：2007-01-09
申请号：KR1020050045385
申请日：2005-05-30
Applicant: 삼성전자주식회사
IPC: H01L21/8242
CPC classification number: H01L21/31138 , B08B7/00 , B08B7/0035 , G03F7/427 , H01L28/91
Abstract: 하부전극의 열화 및 공정 시간의 증가 없이 개구 내에 잔류하는 포토레지스트를 제거하는 포토레지스트 제거 방법 및 이를 이용한 반도체 소자의 제조방법이 개시되어 있다. 포토레지스트가 잔류하는 기판의 표면으로 오존 증기를 제공한 후 상기 오존 증기를 이용하여 상기 기판에 잔류하는 포토레지스트를 산화 분해시킨다. 이후 린스 공정을 수행함으로써 산화 분해된 포토레지스트는 기판으로부터 모두 제거된다. 상기 방법은 기판의 손상 및 열화 없이 포토레지스트 패턴을 보다 빠른 시간 내에 깨끗이 제거할 수 있다.
Abstract translation: 公开了用于去除残留在开口中的光致抗蚀剂而不损坏下电极并且增加处理时间的光致抗蚀剂去除方法以及使用该方法制造半导体装置的方法。 将臭氧蒸汽供应到其上留有光刻胶的衬底表面，并且使用臭氧蒸气氧化分解残留在衬底上的光刻胶。 之后，通过执行漂洗过程从衬底去除氧化物分解的光致抗蚀剂。 该方法可以在较短的时间内干净地去除光致抗蚀剂图案而不损坏和劣化基板。
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公开(公告)号：KR101782329B1
公开(公告)日：2017-09-28
申请号：KR1020110106461
申请日：2011-10-18
Inventor： 홍영택 , 임정훈 , 이진욱 , 정찬진 , 한훈 , 박재완 , 박성환 , 이양화 , 윤병문 , 엄대홍 , 배상원 , 정지훈 , 김경현 , 김경환 , 문창섭 , 차세호 , 고용선
IPC: C09K13/04 , C09K13/00 , H01L21/306
CPC classification number: H01L21/02658 , C09K13/04 , C09K13/06 , C23F1/16 , H01L21/31111 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
Abstract: 식각용조성물이제공된다. 본발명에따른식각용조성물은인산, 암모늄이온및 실리콘원자, 상기실리콘원자에직접적으로결합하는아미노기를포함하는원자단및 상기실리콘원자에결합된적어도 2개이상의산소원자들을포함하는실리콘화합물을포함할수 있다.
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公开(公告)号：KR1020130059821A
公开(公告)日：2013-06-07
申请号：KR1020110126013
申请日：2011-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/66833 , H01L27/11582 , H01L29/4234 , H01L29/7926 , H01L21/823487
Abstract: PURPOSE: Semiconductor memory devices and a method for fabricating the same are provided to prevent the deterioration of electrical properties due to voids by minimizing the generation of the voids in a gate. CONSTITUTION: A mold stack consisting of an insulating layer(110) and a sacrificial layer is formed on a substrate(101). A mold stack includes a vertical channel(140) formed on the substrate. A first space(108) is formed in the edge of the mold stack. A second space(109) is formed in the central part of the mold stack. A gate(160) filling the first and second spaces is formed. An information storage layer(150) is formed between the gate and the vertical channel.
Abstract translation: 目的：提供半导体存储器件及其制造方法，以通过最小化栅极中的空隙的产生来防止由空隙引起的电特性的劣化。 构成：在基板（101）上形成由绝缘层（110）和牺牲层构成的模堆。 模具堆叠包括形成在基板上的垂直通道（140）。 第一空间（108）形成在模具堆叠的边缘中。 第二空间（109）形成在模具堆叠的中心部分。 形成填充第一和第二空间的门（160）。 信息存储层（150）形成在栅极和垂直沟道之间。
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Patent Agency Ranking
公开(公告)号：KR1020070036465A
公开(公告)日：2007-04-03
申请号：KR1020050091501
申请日：2005-09-29
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76232 , H01L29/66477
Abstract: 돌출된 소자분리막을 갖는 반도체소자의 제조방법을 제공한다. 이 방법은 반도체기판 내에 역경사진 측벽 프로파일을 갖고 상기 반도체기판으로부터 돌출된 예비 소자분리막을 형성하는 것을 구비한다. 상기 예비 소자분리막의 돌출부의 측벽 상에 측벽보호패턴을 형성한다. 상기 측벽보호패턴을 제거하여 메인 소자분리막을 형성한다. 이때, 상기 메인 소자분리막의 돌출부의 측벽이 상기 반도체기판의 상부면에 대하여 수직한 프로파일을 갖도록 한다.
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公开(公告)号：KR1020070000605A
公开(公告)日：2007-01-03
申请号：KR1020050056082
申请日：2005-06-28
Applicant: 삼성전자주식회사
CPC classification number: G03F7/423 , G03F7/422 , H01L21/31133 , H01L21/31138 , H01L27/10814 , H01L27/10855 , H01L28/90
Abstract: A photoresist treatment method for removing hydrophobic group from photoresist monomer is provided to clearly and promptly remove photoresist film from a substrate without damage or deterioration of the substrate by eliminating hydrophobic group from the photoresist monomer coated on the substrate using the first material produced by using water vapor and ozone. The treatment method comprises the steps of: using water vapor and ozone gas to generate first material which eliminates hydrophobic property of the group from photoresist monomer; washing the photoresist free from hydrophobic group with a rinsing material then converting the photoresist into water soluble photoresist. The monomer includes acryl or methacyl based polymer having a main skeleton consisting of carbon and carbon single bonds. The photoresist removal process comprises the steps of: eliminating the hydrophobic group from the photoresist monomer; adding a photoresist washing solution to the photoresist free from the hydrophobic group to form the water soluble photoresist; and rinsing the water soluble photoresist with water to remove the photoresist from a substrate.
Abstract translation: 提供了用于从光致抗蚀剂单体中除去疏水基团的光致抗蚀剂处理方法，通过使用通过使用水制备的第一种材料，从涂布在基材上的光致抗蚀剂单体除去疏水基团，从基材中清除并迅速地除去基材的光致抗蚀剂膜而不损坏或劣化基材 蒸汽和臭氧。 处理方法包括以下步骤：使用水蒸气和臭氧气体产生第一种材料，其消除基团的光致抗蚀剂单体的疏水性; 用漂洗材料洗涤不含疏水基团的光致抗蚀剂，然后将光致抗蚀剂转化为水溶性光致抗蚀剂。 单体包括具有由碳和碳单键组成的主骨架的丙烯酰基或甲基酰基聚合物。 光致抗蚀剂去除方法包括以下步骤：从光致抗蚀剂单体中除去疏水基团; 将光致抗蚀剂洗涤溶液添加到不含疏水基团的光致抗蚀剂上以形成水溶性光致抗蚀剂; 并用水冲洗水溶性光致抗蚀剂以从基底上除去光致抗蚀剂。
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公开(公告)号：KR102031182B1
公开(公告)日：2019-10-14
申请号：KR1020110126013
申请日：2011-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
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公开(公告)号：KR1020130078459A
公开(公告)日：2013-07-10
申请号：KR1020110147419
申请日：2011-12-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/7827 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/7926 , H01L27/0688
Abstract: PURPOSE: A non-volatile memory device of a vertical structure and a method for manufacturing the same are provided to increase the degree of integration by forming a unit string in a semiconductor layer pattern. CONSTITUTION: A semiconductor layer pattern (469) is extended in a vertical direction on a substrate. A gate pattern (500) is alternatively laminated along one sidewall of the semiconductor layer pattern. An interlayer dielectric layer pattern (420) is alternatively laminated along the one sidewall of the semiconductor layer pattern. A storage structure is formed between the gate pattern and the semiconductor layer pattern. The recess surface of the gate pattern is vertical to the surface of a substrate.
Abstract translation: 目的：提供垂直结构的非易失性存储器件及其制造方法，以通过以半导体层图案形成单位串来提高积分度。 构成：半导体层图案（469）在基板上沿垂直方向延伸。 沿着半导体层图案的一个侧壁交替层叠栅极图案（500）。 沿着半导体层图案的一个侧壁交替层叠层间电介质层图案（420）。 在栅极图案和半导体层图案之间形成存储结构。 栅极图案的凹部表面垂直于衬底的表面。
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公开(公告)号：KR1020120110452A
公开(公告)日：2012-10-10
申请号：KR1020110028320
申请日：2011-03-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11578 , H01L21/823487 , H01L27/0688 , H01L27/11582 , H01L29/7926
Abstract: PURPOSE: A 3D semiconductor memory device and manufacturing method thereof are provided to prevent the resistance of an electrode by minimizing the etching loss of the highest electrode. CONSTITUTION: An electrode structure includes stacked electrodes and an insulating pattern. A work electrode includes a first outer sidewall and a second outer sidewall facing each other. A vertical active pattern(120) passes through the electrode structure. An electrode dielectric layer(170) is interposed between each electrode. The electrode dielectric layer is located between the sidewalls of the vertical active pattern.
Abstract translation: 目的：提供一种3D半导体存储器件及其制造方法，以通过最小化最高电极的蚀刻损耗来防止电极的电阻。 构成：电极结构包括堆叠电极和绝缘图案。 工作电极包括彼此面对的第一外侧壁和第二外侧壁。 垂直有源图案（120）穿过电极结构。 在每个电极之间插入电极介电层（170）。 电极介电层位于垂直有源图案的侧壁之间。
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