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公开(公告)号：KR102137375B1
公开(公告)日：2020-07-24
申请号：KR1020130124693
申请日：2013-10-18
Applicant: 삼성전자주식회사 , 인터내셔널 비즈니스 머신즈 코오퍼레이션
IPC: H01L21/336 , H01L29/78
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公开(公告)号：KR1020150004724A
公开(公告)日：2015-01-13
申请号：KR1020130124693
申请日：2013-10-18
Applicant: 삼성전자주식회사 , 인터내셔널 비즈니스 머신즈 코오퍼레이션
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66636 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/7834 , H01L29/7848
Abstract: 스트레인드 실리콘(Strained Si) 공정 중 하나인 내장된 소오스/드레인(embedded source/drain)을 형성하기 전에 진행되는 리세스 형성 과정에서 희생 에피택셜막을 이용함으로써, 첨단(tip)이 채널 영역에 근접하는 리세스를 형성하고, 누설 전류를 개선할 수 있는 반도체 소자 제조 방법을 제공하는 것이다. 상기 반도체 소자 제조 방법은 기판 상에 게이트 패턴을 형성하고, 상기 게이트 패턴의 측면에, 상기 기판에서 돌출되는 희생 에피택셜막을 형성하고, 상기 희생 에피택셜막 및 상기 기판을 식각하여, 상기 게이트 패턴의 측면에 제1 리세스를 형성하는 것을 포함한다.
Abstract translation: 本发明涉及一种用于制造半导体器件的方法，该半导体器件改善漏电流并且允许尖端通过在形成嵌入式源极/漏极之前执行的凹陷形成工艺中使用牺牲性外延层来形成与沟道区相邻的凹部 ，这是应变Si工艺之一。 制造半导体器件的方法包括在衬底上形成栅极图案，形成在栅极图案侧从衬底突出的牺牲性外延层，蚀刻牺牲外延层和衬底，并且在第 侧面图案。
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公开(公告)号：KR1020090111932A
公开(公告)日：2009-10-28
申请号：KR1020080037556
申请日：2008-04-23
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
Abstract: PURPOSE: A gate structures and a method of forming the same are provided to improve the thermal stability and the electrical characteristic by forming an Ohmic layer pattern with a high melting point metal like the titanium. CONSTITUTION: A gate structure comprises a gate insulating layer(110) on a substrate, a poly silicon layer on the gate insulating layer, an Ohmic layer on the poly silicon layer, a diffusion barrier on the Ohmic layer, an amorphous silicon on the diffusion barrier, and a metal layer on the amorphous silicon. The method of manufacturing a gate structure is as follows. The gate insulating layer is formed on the substrate. The poly silicon layer is formed on the gate insulating layer. The Ohmic layer is formed on the poly silicon layer. The diffusion barrier is formed on the Ohmic layer. The amorphous silicon layer is formed on the diffusion barrier. The metal layer is formed on the amorphous silicon layer.
Abstract translation: 目的：提供一种栅极结构及其形成方法，以通过形成具有像钛这样的高熔点金属的欧姆层图案来提高热稳定性和电特性。 构成：栅极结构包括在基板上的栅极绝缘层（110），栅极绝缘层上的多晶硅层，多晶硅层上的欧姆层，欧姆层上的扩散阻挡层，扩散层上的非晶硅 阻挡层和非晶硅上的金属层。 栅极结构的制造方法如下。 栅极绝缘层形成在基板上。 多晶硅层形成在栅极绝缘层上。 欧姆层形成在多晶硅层上。 扩散阻挡层在欧姆层上形成。 在扩散阻挡层上形成非晶硅层。 金属层形成在非晶硅层上。
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公开(公告)号：KR100725369B1
公开(公告)日：2007-06-07
申请号：KR1020050134428
申请日：2005-12-29
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: 반도체 기판과 반도체 기판 상에 형성된 도우프된 도전막을 포함하는 반도체 소자가 제공된다. 확산 배리어막이 도우프된 도전막 상에 형성된다. 확산 배리어막은 비정질 반도체 물질을 포함한다. 오믹 콘택막이 확산 배리어막 상에 형성된다. 금속 배리어막이 오믹 콘택막 상에 형성된다. 금속막이 금속 배리어막 상에 형성된다.
비정질 실리콘막, 불순물이 도우프된 다결정 실리콘막, 반전 커패시턴스-
公开(公告)号：KR1020060132220A
公开(公告)日：2006-12-21
申请号：KR1020050052443
申请日：2005-06-17
Applicant: 삼성전자주식회사
IPC: H01L21/24
CPC classification number: H01L21/28518 , H01L21/02175 , H01L21/32055 , H01L21/324 , H01L21/823437
Abstract: A method for forming a silicide layer and a method for forming a gate electrode using the same are provided to reduce the thickness of the silicide layer and to restrain the growth of agglomeration by nitridation treatment. A preliminary metal film for forming silicide is formed on a silicon substrate(200). The upper portion of the preliminary metal film is treated by nitridation processing to reduce the thickness of the preliminary metal film, thereby changing a metal nitride layer(208a) and forming a metal film with a relatively thin thickness compared to the preliminary metal film. The metal film is changed to a silicide layer(212a) by annealing the resultant structure.
Abstract translation: 提供了形成硅化物层的方法和使用其形成栅电极的方法，以减小硅化物层的厚度并通过氮化处理来抑制附聚生长。 在硅衬底（200）上形成用于形成硅化物的初步金属膜。 通过氮化处理来对初级金属膜的上部进行处理以减小初级金属膜的厚度，从而与初步金属膜相比，改变金属氮化物层（208a）并形成厚度相对较薄的金属膜。 通过退火所得到的结构，将金属膜改变为硅化物层（212a）。
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Patent Agency Ranking
公开(公告)号：KR100654358B1
公开(公告)日：2006-12-08
申请号：KR1020050073415
申请日：2005-08-10
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: A semiconductor integrated circuit device is provided to optimizing the capabilities of an N-type transistor and a P-type transistor by selectively forming an ohmic layer only in an N-type transistor whereas the ohmic layer is not formed in a P-type transistor. An N-type transistor region and a P-type transistor region are defined in a substrate(105). An N-type transistor(100) is formed in the N-type transistor region wherein a source/drain region(160), polysilicon and a metal layer(136) are stacked in the N-type transistor, including a gate electrode having an ohmic layer(132) and a barrier layer(134) between the polysilicon and the metal layer. A P-type transistor(101) is formed in the P-type transistor region wherein polysilicon and a metal layer are stacked in the P-type transistor, including a gate electrode having a barrier layer between the polysilicon and the metal layer. The polysilicon of the N-type transistor is N-type polysilicon(120N), and the polysilicon of the P-type transistor is P-type polysilicon(120P).
Abstract translation: 提供半导体集成电路器件以通过仅在N型晶体管中选择性地形成欧姆层而不在P型晶体管中形成欧姆层来优化N型晶体管和P型晶体管的能力。 N型晶体管区域和P型晶体管区域被限定在衬底（105）中。 在N型晶体管区域中形成N型晶体管（100），其中在N型晶体管中堆叠源极/漏极区域（160），多晶硅和金属层（136），所述N型晶体管包括具有 欧姆层（132）和位于多晶硅和金属层之间的阻挡层（134）。 在其中多晶硅和金属层堆叠在P型晶体管中的P型晶体管区域中形成P型晶体管（101），该P型晶体管包括在多晶硅和金属层之间具有阻挡层的栅电极。 N型晶体管的多晶硅为N型多晶硅（120N），P型晶体管的多晶硅为P型多晶硅（120P）。
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公开(公告)号：KR101556238B1
公开(公告)日：2015-10-01
申请号：KR1020090012973
申请日：2009-02-17
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/20
CPC classification number: H01L27/10891
Abstract: 선택적증착법을이용한매립형배선라인을구비하는반도체소자의제조방법을개시한다. 반도체기판에트렌치를형성한다. 제1도전막을상기트렌치의측면및 저면에형성한다. 상기트렌치에매립되도록제2도전막을선택적증착법을이용하여상기제1도전막상에선택적으로형성한다. 상기제2도전막을형성하는것은무전해도금법을이용하여형성하는것 또는 MOCVD 또는 ALD 증착법을이용하여형성하는것을포함할수 있다.
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公开(公告)号：KR101516157B1
公开(公告)日：2015-04-30
申请号：KR1020080037556
申请日：2008-04-23
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
Abstract: 게이트구조물은기판상의게이트절연막, 게이트절연막상의폴리실리콘막, 폴리실리콘막상의오믹막, 오믹막상의확산방지막, 확산방지막상의비정질막및 비정질막상의금속막을포함한다. 게이트구조물은낮은면저항및 우수한열적안정성을갖는다.
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公开(公告)号：KR1020100093859A
公开(公告)日：2010-08-26
申请号：KR1020090012973
申请日：2009-02-17
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/20
CPC classification number: H01L27/10891
Abstract: PURPOSE: The manufacturing method of the semiconductor device having imbedded wiring line selectively forms the low resistance wiring material on the barrier film by using the optional deposition. The imbedded wiring line is formed within the trench. CONSTITUTION: The pad insulating film(120) and hard mask layer(140) are formed on the semiconductor substrate(110). The buffer layer(130) is formed between the pad insulating film and hard mask layer. The active area of the semiconductor substrate is etched and the trench(150) is formed. The first conductive film is formed in the side and bottom surface of the trench. The second conductive film is selectively formed in the first conductive film in order to be buried to the trench.
Abstract translation: 目的：具有嵌入布线的半导体器件的制造方法通过使用任选的沉积在阻挡膜上选择性地形成低电阻布线材料。 嵌入的布线形成在沟槽内。 构成：在半导体衬底（110）上形成衬垫绝缘膜（120）和硬掩模层（140）。 缓冲层（130）形成在焊盘绝缘膜和硬掩模层之间。 蚀刻半导体衬底的有源区，形成沟槽（150）。 第一导电膜形成在沟槽的侧表面和底表面中。 第二导电膜选择性地形成在第一导电膜中以便被埋入到沟槽中。
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公开(公告)号：KR1020090132801A
公开(公告)日：2009-12-31
申请号：KR1020080058959
申请日：2008-06-23
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/4933 , H01L21/28061 , H01L27/10873
Abstract: PURPOSE: A gate structure, a forming method thereof, and a semiconductor device including the same are provided to prevent the increase of the sheet resistance of a metal film by forming a nitrification prevention film between a metal film and a nitrification film mask. CONSTITUTION: A gate insulation film(105) is formed on a substrate(100). A polysilicon film(110) is formed on the gate insulation film. A metal film(120) is formed on the polysilicon film. The metal silicide nitrification film is formed on the metal film. The metal silicide nitrification film includes one of tungsten, tantalum, titanium, cobalt, molybdenum, hafnium, ad nickel. The thickness of the metal silicide nitrification film is 5 to 100 angstrom.
Abstract translation: 目的：提供一种栅极结构及其形成方法和包括该栅极结构的半导体器件，以通过在金属膜和硝化膜掩模之间形成防硝化膜来防止金属膜的薄层电阻增加。 构成：在基板（100）上形成栅极绝缘膜（105）。 在栅极绝缘膜上形成多晶硅膜（110）。 在多晶硅膜上形成金属膜（120）。 金属硅化物硝化膜形成在金属膜上。 金属硅化物硝化膜包括钨，钽，钛，钴，钼，铪，镍中的一种。 金属硅化物硝化膜的厚度为5〜100埃。
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