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公开(公告)号：KR1020030047387A
公开(公告)日：2003-06-18
申请号：KR1020010077864
申请日：2001-12-10
Applicant: 삼성전자주식회사
IPC: H01L27/04
Abstract: PURPOSE: A method for forming patterns of a semiconductor device and a semiconductor device thereby are provided to prevent the critical dimension or a forming error of width of semi-dense patterns or isolated patterns by forming PPC dummy patterns on a side portion of the semi-dense patterns or the isolated patterns. CONSTITUTION: A plurality of main patterns(32,34,36) are formed on a semiconductor substrate. A plurality of PPC dummy patterns(38,40) are formed on a side portion of the main patterns in order to prevent a damage of the main patterns. The PPC dummy patterns and the main patterns are simultaneously formed by using a photo-lithography method. A gate electrode is formed by the main patterns. An interval between the PPC dummy patterns and the main patterns is less than 3 micrometers.
Abstract translation: 目的：提供一种用于形成半导体器件和半导体器件的图案的方法，以通过在半导体器件的侧部上形成PPC虚拟图案来防止半致密图案或孤立图案的宽度的临界尺寸或成形误差， 密集图案或孤立图案。 构成：在半导体衬底上形成多个主图案（32,34,36）。 为了防止主图案的损坏，在主图案的侧部形成有多个PPC虚拟图案（38,40）。 通过使用光刻法同时形成PPC虚拟图案和主图案。 栅电极由主图形形成。 PPC虚拟图案与主图案之间的间隔小于3微米。
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公开(公告)号：KR100083997B1
公开(公告)日：1995-04-13
申请号：KR1019910015605
申请日：1991-09-06
Applicant: 삼성전자주식회사
IPC: H01L27/108
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公开(公告)号：KR100082519B1
公开(公告)日：1995-02-20
申请号：KR1019910020705
申请日：1991-11-20
Applicant: 삼성전자주식회사
IPC: H01L21/3205
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公开(公告)号：KR1019930011263A
公开(公告)日：1993-06-24
申请号：KR1019910021689
申请日：1991-11-29
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: 반도체 기판(20) 상에 필드 산화막(21), 게이트전극(23), 이온주입을 통한 소오스 드레인 부순물 영역(22,22'), 층간 절연막(24)을 차례로 형성하고 그 상부에 대략 U자 형상의 스토리지 노드 폴리 실리콘층(26)을 형성하고, 그 스토리지 폴리의 외면을 절연막(28)으로 피복하고 그 절연막 외면에는 플레이트 폴리 실리콘층(29)을 형성하는 구성을 가짐으로써, 커패시터 용량이 더욱 증대하게 되었고, 아울러 그 제조방법 또한 간단하게 한다.
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Patent Agency Ranking
公开(公告)号：KR1019930011249A
公开(公告)日：1993-06-24
申请号：KR1019910019682
申请日：1991-11-06
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: 내용 없음
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公开(公告)号：KR1019920008149B1
公开(公告)日：1992-09-22
申请号：KR1019890011387
申请日：1989-08-10
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: The method for minimizing device isolation regions to reduce the chip size uses forming an oxide film in the inner part of trench to isolate between the devices, there by increasing the breakdown voltage between the devices. The method comprises forming an oxide film (23), a polysilicon film (25), a nitride film (27) and an oxide film (29) onto a substrate (21) to form openings (31a,31b) therein, forming trenches (33a,33b) through the openings to form ion implantation regions (35a,35b), removing the films (29,27) to form an oxide film (37), a polysilicon film (39), an oxide film (41) and a planar film (43) on the film (25) and trenches, forming an oxide film (45) and a planar film (47) and forming diffusion regions (36a,36b).
Abstract translation: 用于最小化器件隔离区域以减小芯片尺寸的方法使用在沟槽的内部部分形成氧化膜以在器件之间隔离，通过增加器件之间的击穿电压。 该方法包括在基板（21）上形成氧化膜（23），多晶硅膜（25），氮化物膜（27）和氧化膜（29），以在其中形成开口（31a，31b），形成沟槽 33a，33b）通过开口形成离子注入区（35a，35b），去除膜（29,27）以形成氧化膜（37），多晶硅膜（39），氧化膜（41）和 平面膜（43）和沟槽，形成氧化物膜（45）和平面膜（47）并形成扩散区域（36a，36b）。
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公开(公告)号：KR101560332B1
公开(公告)日：2015-10-15
申请号：KR1020090014451
申请日：2009-02-20
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: G03F1/36
Abstract: 본발명은마스크및 마스크의형성의형성방법을제공한다. 이방법은타겟패턴을설정하는단계, 타켓패턴에의해형성된사이드로브의발생을확인하는단계, 타겟패턴및 사이드로브가발생한영역에예비타켓패턴및 예비사이드로브패턴을설정하는단계, 예비타켓패턴및 예비사이드로브패턴을이용하여간섭패턴맵(map)을생성하는단계, 간섭패턴맵에서상기예비타켓패턴의위치의위상과같은위상또는반대위상을가지는영역들중의적어도하나를간섭보조패턴들로설정하는단계, 및간섭보조패턴들및 타겟패턴들을이용하여마스크를형성하는단계를포함한다.
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