公开(公告)号：KR101443063B1

公开(公告)日：2014-09-24

申请号：KR1020080069681

申请日：2008-07-17

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  이종원 ,  홍창기 ,  윤보언

IPC: H01L21/31 ,  H01L27/105

CPC classification number: H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

Abstract: 향상된 특성을 갖는 강유전체 박막의 제조 방법 및 이를 이용한 반도체 장치의 제조 방법이 개시된다. 기판 상에 유기 금속 화학 기상 증착 공정으로 PZT를 증착하여 예비 강유전체막을 형성한 후, 예비 강유전체막의 표면을 아크릴산계 고분자, 연마입자 및 물을 포함하는 슬러리 조성물을 사용하여 화학 기계적으로 연마하여 기판 상에 강유전체 박막을 형성한다. 예비 강유전체막의 연마 속도를 감소시켜 벌크 부분의 연마를 억제하고 표면 거칠기를 개선함으로써, 강유전체 박막을 포함하는 메모리 장치의 전기적 특성 및 내구성을 향상시킬 수 있다.

公开(公告)号：KR1020100057203A

公开(公告)日：2010-05-31

申请号：KR1020080116122

申请日：2008-11-21

Applicant: 삼성전자주식회사

Inventor： 김영후 ,  홍창기 ,  이재동

IPC: H01L21/28

CPC classification number: H01L21/76831 ,  H01L21/76885 ,  H01L27/10855 ,  H01L27/10888

Abstract: PURPOSE: A wiring structure and this formation method of the semiconductor device apply the spacer interviewing in the contact pattern and contact plug. The damage of the contact pattern by the washing solution is prevented. CONSTITUTION: Contact pads(124, 126) are electrically connected to contact areas(116a, 116b) of the substrate(100). The contact plug(150) is electrically connected to the contact pad. The spacer(140) is at the same time face-contacted in the top of the contact pad sidewall and sidewall of the contact plug. The insulating layer pattern(120) has the opening accepting the contact plug and spacer.

Abstract translation: 目的：半导体器件的布线结构和形成方法应用接触图形和接触插头中的间隔件访问。 防止了洗涤液对接触图形的损伤。 构成：接触焊盘（124,126）电连接到衬底（100）的接触区域（116a，116b）。 接触插头（150）电连接到接触垫。 间隔件（140）同时在接触垫侧壁和接触插塞的侧壁的顶部面接触。 绝缘层图案（120）具有接受接触插塞和间隔件的开口。

公开(公告)号：KR1020100009013A

公开(公告)日：2010-01-27

申请号：KR1020080069681

申请日：2008-07-17

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  이종원 ,  홍창기 ,  윤보언

IPC: H01L21/31 ,  H01L27/105

CPC classification number: H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

Abstract: PURPOSE: A method for forming a ferroelectric thin film and a semiconductor device manufacturing method using the same are provided to flatten only rough portion of the ferroelectric thin film while suppressing the abrasion of bulk portion of the ferroelectric thin film by using slurry composition. CONSTITUTION: A conductive structure is formed on a substrate(S110). A pre ferroelectric film is formed on the conductive structure(S120). The surface of the pre ferroelectric film is chemically-mechanically polished using slurry composition(S130). A ferroelectric film with improved surface roughness is washed(S140). The ferroelectric film is heat-treated to cure the damage of the film surface(S150).

Abstract translation: 目的：提供一种形成铁电薄膜的方法及使用该方法的半导体器件制造方法，通过使用浆料组合物来抑制铁电薄膜的本体部分的磨损，使粗铁电薄膜的平坦化。 构成：在基板上形成导电结构（S110）。 在导电结构上形成预铁电体膜（S120）。 使用浆料组合物对预铁电体膜的表面进行化学机械抛光（S130）。 洗涤具有改善的表面粗糙度的铁电体膜（S140）。 对铁电体膜进行热处理以固化膜表面的损伤（S150）。

公开(公告)号：KR1020090116360A

公开(公告)日：2009-11-11

申请号：KR1020080042251

申请日：2008-05-07

Applicant: 삼성전자주식회사

Inventor： 강대혁 ,  김영후 ,  홍창기 ,  이근택 ,  이재동 ,  엄대홍 ,  한정남

IPC: H01L21/28 ,  H01L21/24

CPC classification number: H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/485 ,  H01L27/24 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: PURPOSE: A method for forming a contact structure and the method for manufacturing a semiconductor device using the same are provided to form a metal oxide silicide layer uniformly by performing a silicidation process and forming a metal layer on a material layer including silicon and oxygen. CONSTITUTION: An insulation layer(106) is formed on an object with a contact region(103). An opening is formed to expose a contact region by etching an insulation layer. A material layer containing the silicon and oxygen is formed in the exposed contact region. A metal layer is formed on the material layer containing the silicon and oxygen. A metal oxide silicide layer(121) is formed on a contact region by reacting the material layer with the metal layer. A conductive layer(124) to fill the opening is formed on the metal oxide silicide layer.

Abstract translation: 目的：提供一种用于形成接触结构的方法和使用其的半导体器件的制造方法，以通过在硅和氧的材料层上进行硅化处理和形成金属层来均匀地形成金属氧化物硅化物层。 构成：在具有接触区域（103）的物体上形成绝缘层（106）。 通过蚀刻绝缘层形成开口以暴露接触区域。 在暴露的接触区域中形成含有硅和氧的材料层。 在含有硅和氧的材料层上形成金属层。 通过使材料层与金属层反应，在接触区域上形成金属氧化物硅化物层（121）。 在金属氧化物硅化物层上形成填充开口的导电层（124）。

公开(公告)号：KR1020090062757A

公开(公告)日：2009-06-17

申请号：KR1020070130190

申请日：2007-12-13

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  한상엽 ,  홍창기 ,  윤보언 ,  이재동

IPC: H01L21/283

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

Abstract: A method for manufacturing a semiconductor device is provided to improve a shoulder margin of a capping pattern by forming an upper part of the capping pattern to cover a gate pattern with a planarized profile. An element isolation film(112) defining an active area is formed in a semiconductor substrate(110). A gate insulating layer, a gate conductive film and a mask film are formed on a semiconductor substrate. The mask pattern having an upper profile of the rounded shape is formed by patterning the mask film. The gate pattern is formed by patterning the gate conductive film and the gate insulating film. The gate pattern is comprised between a gate insulating pattern(114) and a gate electrode(116). The upper part and the sidewall of the gate pattern are covered with the capping pattern. An interlayer insulating film(124) is formed to expose the upper part of the capping pattern. The capping pattern with the planarized upper profile is formed by polishing the interlayer insulating film and the capping pattern.

Abstract translation: 提供一种用于制造半导体器件的方法，通过形成覆盖图案的上部以覆盖具有平坦化轮廓的栅极图案来改善封盖图案的肩部边缘。 在半导体衬底（110）中形成限定有源区的元件隔离膜（112）。 在半导体衬底上形成栅极绝缘层，栅极导电膜和掩模膜。 通过对掩模膜进行图案化而形成具有圆形形状的上轮廓的掩模图案。 栅极图案通过对栅极导电膜和栅极绝缘膜进行图案化而形成。 栅极图案包括在栅极绝缘图案（114）和栅极电极（116）之间。 栅极图案的上部和侧壁被覆盖图案覆盖。 形成层间绝缘膜（124）以露出封盖图案的上部。 通过抛光层间绝缘膜和封盖图案形成具有平坦化上表面的封盖图案。

公开(公告)号：KR1020090038079A

公开(公告)日：2009-04-20

申请号：KR1020070103367

申请日：2007-10-15

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  신성호 ,  윤보언 ,  홍창기

IPC: H01L21/304 ,  H01L21/66

CPC classification number: B24B9/065 ,  B24B21/02 ,  B24B37/013 ,  B24B49/12

Abstract: An apparatus for a polishing wafer bevel portion and a method for detecting an end point are provided to detect an end time of the polishing by reliving the load of a calculation process. A wafer polishing apparatus comprises a grinding tape(94), a polishing head(70), and a color image sensor(80). A wafer polishing apparatus comprises a controller, and the grinding tape has the penetrating power of a color image. The grinding tape is made of one of an alumina group, diamond, silica, ceria, silicon carbide. The grinding tape is guided with guide rollers(90,91). A polishing head supports a pusher pad which is faced with the polished surface of the wafer(2) and supports the grinding tape(94). The pusher pad is received into an accommodation space inside the polishing head, and the polishing head is connected to the pushing load(60). The pushing load is coupled with a piston shaft inside a cylinder(50) and the pushing load.

Abstract translation: 提供一种用于抛光晶片斜面部分的装置和用于检测端点的方法，以通过重新计算处理的负载来检测抛光的结束时间。 晶片抛光装置包括研磨带（94），抛光头（70）和彩色图像传感器（80）。 晶片抛光装置包括控制器，并且研磨带具有彩色图像的穿透力。 研磨带由氧化铝组，金刚石，二氧化硅，二氧化铈，碳化硅之一制成。 研磨带用导辊（90,91）引导。 抛光头支撑面对晶片（2）的抛光表面并支撑研磨带（94）的推动垫。 推动垫被容纳在抛光头内部的容纳空间中，并且抛光头连接到推压负载（60）。 推动载荷与缸体（50）内的活塞轴和推动载荷相结合。

公开(公告)号：KR100881181B1

公开(公告)日：2009-02-05

申请号：KR1020060111879

申请日：2006-11-13

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  백인규 ,  이준영 ,  김중현 ,  홍창기 ,  손윤호

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L28/20 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.

公开(公告)号：KR1020090003767A

公开(公告)日：2009-01-12

申请号：KR1020070066700

申请日：2007-07-03

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  홍창기 ,  윤보언 ,  고영호 ,  유동철 ,  임종흔

IPC: G01R1/067

CPC classification number: G01R1/067 ,  H01L21/02 ,  H01L21/302 ,  H01L21/78

Abstract: A method for manufacturing a semiconductor device with tapered patterns is provided to form columnar patterns on a surface of a donor wafer by using a bonding process and a cleaving process. An acceptor wafer and a donor wafer(200') are prepared. The acceptor wafer includes a first pattern and a second pattern made of the material different from the first pattern. The donor wafer includes the hydrogen ion implantation region. The respective first and second bonding areas are formed in the hydrogen ion implantation region of the donor wafer corresponding to the first and second patterns of the acceptor wafer by bonding the accepter wafer and the donor wafer. The bonding strength of the first bonding area is greater than the second bonding area. The first bonding area is separated from the donor wafer by separating the acceptor wafer and the donor wafer. The second bonding area is exposed while being adhered to the donor wafer and is protruded from the donor wafer. The exposed second bonding area is etched and the tapered pattern is formed in the donor wafer.

Abstract translation: 提供了一种用于制造具有锥形图案的半导体器件的方法，以通过使用接合工艺和切割工艺在施主晶片的表面上形成柱状图案。 制备受体晶片和施主晶片（200'）。 受主晶片包括由不同于第一图案的材料制成的第一图案和第二图案。 施主晶片包括氢离子注入区域。 相应的第一和第二接合区域通过接合接收晶片和施主晶片而形成在施主晶片的氢离子注入区域中，其对应于受主晶片的第一和第二图案。 第一接合区域的接合强度大于第二接合面积。 通过分离受体晶片和施主晶片，将第一结合区域与施主晶片分离。 第二接合区域在被粘附到施主晶片的同时被暴露并且从施主晶片突出。 蚀刻暴露的第二接合区域，并且在施主晶片中形成锥形图案。

公开(公告)号：KR100840785B1

公开(公告)日：2008-06-23

申请号：KR1020070016427

申请日：2007-02-16

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  배대록 ,  윤성규 ,  최석헌

IPC: H01L21/31

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8221

Abstract: A method for forming a single crystal silicon pattern in a stacked semiconductor device is provided to simplify a pattern forming process by forming the single crystal silicon pattern without using a photolithography process. A hydrogen ion is implanted on an upper surface of a first substrate(100), which is made of a single crystal silicon, such that a hydrogen ion implantation region(102) is formed at a portion displaced from the upper surface of the first substrate. A silicon oxide film pattern is formed to cover the second substrate on a second substrate, which is made of a single crystal signal. An upper surface of the silicon oxide film pattern is partially protruded. The upper surface of the silicon oxide film pattern, which is formed on the second substrate, is bonded with the upper surface of the first substrate. A portion of the first substrate is separated from the second substrate by using the hydrogen ion implantation region as a cutting surface. A single crystal silicon pattern is selectively formed on the silicon oxide pattern.

Abstract translation: 提供了一种用于在层叠半导体器件中形成单晶硅图案的方法，以通过在不使用光刻工艺的情况下形成单晶硅图案来简化图案形成处理。 在由单晶硅制成的第一衬底（100）的上表面上注入氢离子，使得在从第一衬底的上表面偏移的部分形成氢离子注入区（102） 。 在由单晶信号制成的第二基板上形成氧化硅膜图形以覆盖第二基板。 氧化硅膜图案的上表面部分地突出。 形成在第二基板上的氧化硅膜图案的上表面与第一基板的上表面接合。 通过使用氢离子注入区域作为切割表面，第一衬底的一部分与第二衬底分离。 在氧化硅图案上选择性地形成单晶硅图案。

公开(公告)号：KR1020080040824A

公开(公告)日：2008-05-09

申请号：KR1020060108651

申请日：2006-11-06

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  차용원 ,  홍창기 ,  윤보언 ,  윤성규

IPC: H01L21/76

CPC classification number: H01L21/76294 ,  H01L21/02675

Abstract: A method for isolating a semiconductor device is provided to avoid generation of a void and seam in an insulation layer functioning as an isolation layer by forming an active region after an insulation layer for defining a field region is formed on a substrate. An insulation layer pattern(112) is formed on a single crystal silicon substrate(100), exposing the single crystal substrate and having an opening whose width gradually decreases as it goes downward. An amorphous silicon pattern is formed to fill the opening. A laser beam is irradiated to the amorphous silicon pattern to transform the crystalline structure of the amorphous silicon pattern into a single crystal structure so that an active region made of a single crystal silicon pattern(122) is formed such that the active region is electrically insulated by the insulation layer pattern. The active region can have substantially the same height as that of the upper surface of the insulation layer pattern.

Abstract translation: 提供了用于隔离半导体器件的方法，以避免在用作限定场区域的绝缘层在衬底上形成有源区域之后，在用作隔离层的绝缘层中产生空隙和接缝。 绝缘层图案（112）形成在单晶硅衬底（100）上，暴露单晶衬底并具有宽度随着其下降而逐渐减小的开口。 形成非晶硅图形以填充开口。 将激光束照射到非晶硅图案，以将非晶硅图案的晶体结构转变为单晶结构，从而形成由单晶硅图案（122）制成的有源区，使得有源区电绝缘 通过绝缘层图案。 有源区可以具有与绝缘层图案的上表面大致相同的高度。