公开(公告)号：KR1020040107354A

公开(公告)日：2004-12-20

申请号：KR1020040006611

申请日：2004-02-02

Applicant: 삼성전자주식회사

Inventor： 이주원 ,  추강수 ,  박재언 ,  양종호

IPC: H01L21/20

CPC classification number: C23C16/402 ,  C23C16/45534

Abstract: PURPOSE: A method of forming a silicon dioxide layer and a semiconductor device thereby are provided to obtain precisely controlled surface characteristics from the silicon dioxide layer by using a silicon compound with at least two silicon atoms as a reactant. CONSTITUTION: A functionalized surface of a substrate is exposed to a first compound consisting of a first reactant and a first catalyst(132). A silicon dioxide unit layer is formed on the functionalized surface of the substrate by exposing the resultant structure to a second compound consisting of a second reactant and a second catalyst(136). At this time, at least one or two out of a step (a) to a step (c) have to be utilized. Under the step (a), the first reactant is used, wherein the first reactant contains at least one element selected from a group consisting of silicon compounds with at least two silicon atoms. Under the step (b), the first catalyst is used, wherein the first catalyst contains at least one element selected from a group consisting of tertiary aliphatic amine compounds. Under the step (c), the first reactant and the first catalyst are used in combination with each other.

Abstract translation: 目的：提供一种形成二氧化硅层和半导体器件的方法，以通过使用具有至少两个硅原子的硅化合物作为反应物从二氧化硅层获得精确控制的表面特性。 构成：底物的官能化表面暴露于由第一反应物和第一催化剂（132）组成的第一化合物。 通过将所得结构暴露于由第二反应物和第二催化剂（136）组成的第二化合物，在基板的官能化表面上形成二氧化硅单元层。 此时，必须使用步骤（a）至步骤（c）中的至少一个或两个。 在步骤（a）下，使用第一反应物，其中第一反应物含有至少一种选自具有至少两个硅原子的硅化合物的元素。 在步骤（b）下，使用第一催化剂，其中第一催化剂含有至少一种选自叔脂族胺化合物的元素。 在步骤（c）下，第一反应物和第一催化剂彼此组合使用。

公开(公告)号：KR1020040049174A

公开(公告)日：2004-06-11

申请号：KR1020020077034

申请日：2002-12-05

Applicant: 삼성전자주식회사

Inventor： 이승환 ,  추강수 ,  이주원 ,  박재언 ,  양종호

IPC: H01L21/20

CPC classification number: C23C16/45544 ,  C23C16/4412 ,  C30B25/14 ,  Y10T117/10

Abstract: PURPOSE: ALD(Atomic Layer Deposition) equipment capable of preventing the generation of powder in an exhaust path is provided to prevent a variety of reactants from meeting with each other. CONSTITUTION: ALD equipment is provided with a reaction part(100), a plurality of reactant supply parts(151,155) for alternately supplying reactants to the reaction part, a plurality of exhaust paths installed as many as the same number as the kinds of reactants for independently exhausting each reactant, and exhaust control valves for selectively switching the exhaust paths. Preferably, exhaust paths include pumps(210,250), scrubbers(310,350) installed at the rear end portions of the pumps and exhaust lines(410,431,433,451,453,491,493) for connecting the pumps with the scrubbers and the reaction part.

Abstract translation: 目的：提供能够防止排气路径中产生粉末的ALD（原子层沉积）设备，以防止各种反应物相互碰撞。 构成：ALD设备设有反应部分（100），多个反应物供应部分（151,155），用于将反应物交替地供应到反应部分;多个排气通道，其安装的数量与反应物种类相同， 独立地排出各反应物，排气控制阀用于选择性地切换排气路径。 优选地，排气路径包括安装在泵的后端部分的泵（210,250），用于将泵与洗涤器和反应部分连接的排气管（410,431,433,451,453,491,493）的洗涤器（310,350）。

公开(公告)号：KR1020040014064A

公开(公告)日：2004-02-14

申请号：KR1020020047233

申请日：2002-08-09

Applicant: 삼성전자주식회사

Inventor： 박재언 ,  추강수 ,  이주원 ,  양종호

IPC: H01L21/027

CPC classification number: H01L21/32139 ,  G03F7/40 ,  G03F7/405 ,  H01L21/0274

Abstract: PURPOSE: A method for forming a fine pattern by using a silicon oxide layer is provided to prevent the damage of a photoresist pattern by forming a silicon oxide layer on the photoresist pattern. CONSTITUTION: A photoresist layer is formed on an upper surface of a material layer(110). A photoresist pattern(120) is formed by exposing and developing the photoresist layer. The first silicon oxide layer(130) is formed on each upper surface of the material layer(110) and the photoresist pattern in order to prevent the damage of the photoresist pattern(120). A material layer pattern is formed by dry-etching the material layer(110). The first silicon oxide layer(130) is formed under the temperature of 400 degrees centigrade.

Abstract translation: 目的：提供通过使用氧化硅层形成精细图案的方法，以通过在光致抗蚀剂图案上形成氧化硅层来防止光致抗蚀剂图案的损坏。 构成：光致抗蚀剂层形成在材料层（110）的上表面上。 通过曝光和显影光致抗蚀剂层形成光致抗蚀剂图案（120）。 为了防止光致抗蚀剂图案（120）的损坏，第一氧化硅层（130）形成在材料层（110）和光致抗蚀剂图案的每个上表面上。 通过干蚀刻材料层（110）形成材料层图案。 第一氧化硅层（130）在400℃的温度下形成。

公开(公告)号：KR1020060069754A

公开(公告)日：2006-06-22

申请号：KR1020040108430

申请日：2004-12-18

Applicant: 삼성전자주식회사

Inventor： 추강수 ,  김진현 ,  남명희 ,  이정형 ,  윤관영 ,  엄명윤

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/306

CPC classification number: H01L21/76802 ,  H01L21/31053 ,  H01L21/31111

Abstract: 반도체 소자 제조 방법이 제공된다. 반도체 소자 제조 방법은 반도체 기판 상에 층간 절연막을 형성하고, 제1 CMP를 행하는 단계, 층간 절연막 상에 습식 식각막을 형성한 후, 습식 식각막과 층간 절연막의 소정의 영역을 식각하여 콘택홀들을 형성하는 단계, 콘택홀 내부가 채워지도록 제1 금속을 습식 식각막 전면에 도포한 후, 제2 CMP를 행하여 습식 식각막 상의 제1 금속을 제거하고 그 하부의 습식 식각막과 콘택홀들을 노출시키는 단계, 습식 식각을 통해 노출된 습식 식각막을 선택적으로 제거하여 습식 식각막 하부의 평탄화된 층간 절연막을 노출시키고, 노출된 층간 절연막 상에 금속간 절연막을 도포하고 제3 CMP를 행하여 금속간 절연막 상부를 평탄화 하는 단계를 포함한다.
반도체 소자, 평탄화

公开(公告)号：KR100555552B1

公开(公告)日：2006-03-03

申请号：KR1020040006611

申请日：2004-02-02

Applicant: 삼성전자주식회사

Inventor： 이주원 ,  추강수 ,  박재언 ,  양종호

IPC: H01L21/20

Abstract: 적어도 2개의 실리콘 원자를 가지는 실리콘 화합물로 구성되는 제1 반응물을 사용하거나, 촉매 성분으로서 지방족 3차 아민을 사용하거나, 또는 이들의 조합에 의해 반도체 기판상에 우수한 특성을 가지는 이산화실리콘막을 형성하기 위한 촉매 보조형 원자층 증착 (ALD) 방법과, 이에 관련되는 퍼지 방법 및 시퀀스에 관하여 개시한다.
ALD, 이산화실리콘, 다중 실리콘 화합물, HCD, 지방족 3차 아민

公开(公告)号：KR1020040102656A

公开(公告)日：2004-12-08

申请号：KR1020030034184

申请日：2003-05-28

Applicant: 삼성전자주식회사

Inventor： 이주원 ,  추강수 ,  박재언 ,  양종호

IPC: H01L21/8238

Abstract: PURPOSE: A method for manufacturing a CMOS transistor is provided to simplify photo process by using an SDE(Source/Drain Extension) region. CONSTITUTION: A first and second gate(311,313) are formed on a semiconductor substrate(100) defined by a first and second active region(110,130). A first and second sacrificial spacer are formed at both sidewalls of the first and second gate. An N-type source/drain region(110b) is formed in the first active region by implanting dopants using a first photoresist pattern, the first gate and the first sacrificial spacer as a mask. The first sacrificial spacer is removed, and an N-type source/drain extension region(110a) is formed in the first active region by implanting dopants using the first photoresist pattern and the first gate as a mask. After the first photoresist pattern is removed, a P-type source/drain region(130b) is formed in the second active region by implanting dopants using a second photoresist pattern, the second gate and the second sacrificial spacer as a mask. The second sacrificial spacer is removed, and a P-type source/drain extension region(130a) is formed in the second active region by implanting dopants using the second photoresist pattern and the second gate as a mask.

Abstract translation: 目的：提供一种用于制造CMOS晶体管的方法，以通过使用SDE（源/漏扩展）区域来简化照片处理。 构成：第一和第二栅极（311,313）形成在由第一和第二有源区（110,130）限定的半导体衬底（100）上。 第一和第二牺牲隔离物形成在第一和第二栅极的两个侧壁处。 通过使用第一光致抗蚀剂图案，第一栅极和第一牺牲间隔物作为掩模注入掺杂剂，在第一有源区中形成N型源/漏区（110b）。 去除第一牺牲间隔物，并且通过使用第一光致抗蚀剂图案和第一栅极作为掩模注入掺杂剂，在第一有源区中形成N型源极/漏极延伸区域（110a）。 在去除第一光致抗蚀剂图案之后，通过使用第二光致抗蚀剂图案，第二栅极和第二牺牲间隔物作为掩模注入掺杂剂，在第二有源区中形成P型源/漏区（130b）。 去除第二牺牲间隔物，并且通过使用第二光致抗蚀剂图案和第二栅极作为掩模注入掺杂剂来在第二有源区中形成P型源极/漏极延伸区域（130a）。

公开(公告)号：KR1020040079747A

公开(公告)日：2004-09-16

申请号：KR1020030014779

申请日：2003-03-10

Applicant: 삼성전자주식회사

Inventor： 박재언 ,  추강수 ,  이주원 ,  양종호

IPC: H01L21/8238

CPC classification number: H01L21/823814

Abstract: PURPOSE: A method for fabricating a semiconductor device of an LDD structure is provided to reduce the manufacturing cost by reducing the number of mask patterning processes. CONSTITUTION: A gate insulating layer(22) and a gate electrode(24) are formed on the first and the second conductive transistor regions of a semiconductor substrate(10). The first photoresist pattern for exposing the first conductive transistor region is formed thereon. An LDD region is formed on the first conductive transistor region. The first sacrificial masking layer is formed on the conductive transistor region in order to cover a sidewall of the gate electrode. A source/drain region is formed on the first conductive transistor region. The first sacrificial masking layer and the first photoresist pattern are removed therefrom. An insulating spacer(70) is formed on the sidewall of the gate electrode.

Abstract translation: 目的：提供一种用于制造LDD结构的半导体器件的方法，通过减少掩模图案化工艺的数量来降低制造成本。 构成：在半导体衬底（10）的第一和第二导电晶体管区域上形成栅极绝缘层（22）和栅电极（24）。 用于暴露第一导电晶体管区域的第一光致抗蚀剂图案形成在其上。 在第一导电晶体管区域上形成LDD区。 第一牺牲掩模层形成在导电晶体管区域上以覆盖栅电极的侧壁。 源极/漏极区域形成在第一导电晶体管区域上。 从其中去除第一牺牲掩模层和第一光致抗蚀剂图案。 绝缘间隔物（70）形成在栅电极的侧壁上。

公开(公告)号：KR1020000021347A

公开(公告)日：2000-04-25

申请号：KR1019980040369

申请日：1998-09-28

Applicant: 삼성전자주식회사

Inventor： 추강수 ,  윤태양 ,  황재희

IPC: H01L21/76

Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to prevent a loading effect due to a pattern density when forming a gate electrode, and to secure an etch margin. CONSTITUTION: A method for fabricating a semiconductor device includes a first step through fourth step. The first step is to form an insulating layer pattern(102a) on a semiconductor substrate(100). The second step is to form an insulating layer(104) on the semiconductor substrate including the insulating layer pattern. The third step is to form a conductive layer(106) on the insulating layer. The fourth step is to form a conductive layer pattern(106a-106g) by etching the conductive layer. The iinsulating layer pattern is formed on a relatively wide area(b) between an adjacent conductive layer pattern. Thus, the relatively wide area between the adjacent conductive layer pattern is not exposed on the semiconductor substrate when etching the conductive layer of a relatively narrow area(a) between the adjacent conductive layer patterns.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以防止在形成栅电极时由于图案密度引起的负载效应，并确保蚀刻余量。 构成：制造半导体器件的方法包括第一步至第四步骤。 第一步是在半导体衬底（100）上形成绝缘层图案（102a）。 第二步是在包括绝缘层图案的半导体衬底上形成绝缘层（104）。 第三步是在绝缘层上形成导电层（106）。 第四步骤是通过蚀刻导电层形成导电层图案（106a-106g）。 绝缘层图案形成在相邻导电层图案之间的相对较宽的区域（b）上。 因此，当蚀刻相邻导电层图案之间相对较窄区域（a）的导电层时，相邻导电层图案之间的相对较宽的区域不会暴露在半导体衬底上。

公开(公告)号：KR1020000002043A

公开(公告)日：2000-01-15

申请号：KR1019980022587

申请日：1998-06-16

Applicant: 삼성전자주식회사

Inventor： 추강수 ,  윤태양 ,  이승형 ,  이혁준

IPC: H01L27/108

Abstract: PURPOSE: A semiconductor capacity production method is provided to increase the capacity of a capacitor and to enhance the reliability of a semiconductor element. CONSTITUTION: The semiconductor production method comprises the process of; forming the 1st insulation film(14) on the semiconductor substrate(12) and removing the 1st insulation film(14) to form the 1st contact hole(16); forming a lower electrode material layer(18) on the semiconductor substrate(12) including the 1st contact hole(16) forming a dielectric material(20) and the upper electrode material(22) one after another.

Abstract translation: 目的：提供半导体容量制造方法以增加电容器的容量并提高半导体元件的可靠性。 构成：半导体生产方法包括以下过程： 在所述半导体基板（12）上形成所述第一绝缘膜（14），并移除所述第一绝缘膜（14）以形成所述第一接触孔（16）; 在包括形成电介质材料（20）的第一接触孔（16）和上电极材料（22）的半导体衬底（12）上形成下电极材料层（18）。

公开(公告)号：KR1020060053828A

公开(公告)日：2006-05-22

申请号：KR1020050018345

申请日：2005-03-04

Applicant: 삼성전자주식회사

Inventor： 민재식 ,  하용웅 ,  추강수

IPC: B41J2/05

Abstract: 본 발명은 잉크젯 프린터 헤드에 관한 것으로, 본 발명의 잉크젯 프린터 헤드는 잉크 피드홀이 형성된 기판과, 상기 기판 상의 상기 잉크 피드홀의 주변에 형성된 층간 절연층과, 상기 층간 절연층 상에 금속으로 된 적어도 하나이상의 금속층과, 상기 잉크 피드홀과 상기 금속층 사이에 형성되어 상기 잉크 피드홀의 잉크로부터 습기가 상기 금속층으로 전달되는 것을 방지하는 흡습방지부를 구비한 것으로, 본 발명에 따른 잉크젯 프린터 헤드 및 그 제조방법은 흡습성을 갖는 층으로부터 잉크의 습기가 금속배선층, 로직영역 또는 압력구동부로 침투하는 것을 차단할 수 있기 때문에, 층간 박리, 전기적 쇼트, 회로의 오동작 및 금속배선층 부식과 같은 불량이 발생되는 것을 방지할 수 있게 되고, 이에 따라 헤드의 수명 및 신뢰성을 향상시킬 수 있을 뿐만 아니라, 잉크젯 프린터 헤드의 생산 수율증가로 생산성 증대 및 제조단가를 절감시킬 수 있게 된다.