公开(公告)号：KR1020040103571A

公开(公告)日：2004-12-09

申请号：KR1020030034522

申请日：2003-05-29

Applicant: 삼성전자주식회사

Inventor： 윤선필 ,  최시영 ,  구자흠 ,  이창원 ,  김성만 ,  허성준

IPC: H01L21/336

Abstract: PURPOSE: A semiconductor device having a low-resistance metal polycrystalline silicon gate electrode and a fabricating method thereof are provided to restrain formation of a high-resistance amorphous layer or an insulating layer by forming an interface reaction preventing layer between a polycrystalline silicon layer and a nitride metal barrier layer. CONSTITUTION: A dielectric layer(102) is formed on an upper surface of a semiconductor substrate(100). A polycrystalline silicon layer(104) is formed on the dielectric layer. An interface reaction preventing layer(106) is formed on the polycrystalline silicon layer in order to prevent reaction between the polycrystalline silicon layer and a material layer formed on the polycrystalline silicon layer. A barrier layer(108) is formed on the interface reaction preventing layer. A metal layer is formed on the barrier layer.

Abstract translation: 目的：提供一种具有低电阻金属多晶硅栅电极及其制造方法的半导体器件，用于通过在多晶硅层和多晶硅层之间形成界面反应防止层来抑制形成高电阻非晶层或绝缘层 氮化物金属阻挡层。 构成：在半导体衬底（100）的上表面上形成介电层（102）。 在电介质层上形成多晶硅层（104）。 在多晶硅层上形成界面反应防止层（106），以防止多晶硅层与多晶硅层上形成的材料层之间的反应。 在界面反应防止层上形成阻挡层（108）。 在阻挡层上形成金属层。

公开(公告)号：KR1020030079545A

公开(公告)日：2003-10-10

申请号：KR1020020018618

申请日：2002-04-04

Applicant: 삼성전자주식회사

Inventor： 이창원 ,  최시영 ,  구자흠 ,  허성준 ,  윤선필 ,  김성만 ,  선민철

IPC: H01L21/8242

CPC classification number: H01L29/6656 ,  H01L21/28044 ,  H01L29/4941

Abstract: PURPOSE: A method for manufacturing a semiconductor device including a metal conductive layer is provided to be capable of preventing the surface oxidation of an exposed portion of the metal conductive layer when depositing a silicon oxide layer by sequentially carrying out a pre-flow process and a main flow process using silicon source gas alone or the silicon source gas and oxygen source gas, simultaneously. CONSTITUTION: After forming an exposed metal conductive pattern at the upper portion of a substrate(10), the resultant structure is loaded into a reaction chamber. Then, a pre-flow process is carried out at the resultant structure by using at least silicon source gas in the reaction chamber. After carrying out a main flow process at the resultant structure by using the silicon source gas and oxygen source gas, a silicon oxide layer(22) is formed on the entire surface of the resultant structure.

Abstract translation: 目的：提供一种用于制造包括金属导电层的半导体器件的方法，其能够通过依次进行预流程和沉积氧化硅层而防止金属导电层的暴露部分的表面氧化 主要流程单独使用硅源气体或硅源气体和氧源气体同时进行。 构成：在基板（10）的上部形成露出的金属导电图案之后，将所得结构装入反应室。 然后，通过在反应室中至少使用硅源气体，在所得结构下进行预流程处理。 通过使用硅源气体和氧源气体在所得结构中进行主流程处理之后，在所得结构的整个表面上形成氧化硅层（22）。

公开(公告)号：KR100634163B1

公开(公告)日：2006-10-16

申请号：KR1020030010403

申请日：2003-02-19

Applicant: 삼성전자주식회사

Inventor： 허성준 ,  최시영 ,  최길현 ,  구자흠 ,  이창원 ,  윤선필 ,  김성만 ,  이종명 ,  유권선

IPC: H01L21/336

CPC classification number: H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: 금속 게이트 전극을 구비하는 반도체 소자의 형성 방법을 제공한다. 상기 방법에 따르면, 반도체 기판 상에 게이트 절연막, 게이트 폴리막, 장벽 금속막, 금속 게이트막, 및 캐핑막을 차례로 형성한다. 상기 캐핑막, 상기 금속게이트막, 상기 장벽 금속막, 및 상기 게이트 폴리막을 차례로 패터닝하여 차례로 적층된 게이트 폴리막 패턴, 장벽 금속막 패턴, 금속 게이트막 패턴, 및 캐핑막 패턴으로 이루어지는 게이트 패턴을 형성한다. 상기 금속 게이트막 패턴의 측벽을 덮는 산소차단막을 형성한다.
금속 게이트 전극, 텅스텐

公开(公告)号：KR1020040025479A

公开(公告)日：2004-03-24

申请号：KR1020020057456

申请日：2002-09-19

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  이창원 ,  허성준 ,  윤선필 ,  김성만

IPC: H01L21/28

CPC classification number: H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

Abstract: PURPOSE: A method for manufacturing a semiconductor device with a metal gate pattern is provided to be capable of curing damage by using selective oxidation processing. CONSTITUTION: A metal gate substance including a metal film is deposited on a silicon substrate having a gate insulating layer(S10). A metal gate pattern is formed by etching the metal gate substance(S20). A capping layer is formed on the metal gate pattern(S30). Selective oxidation processing is performed on selectively oxidize silicon-containing substance while restraining oxidation of the metal film for curing damage of the metal gate pattern(S40).

Abstract translation: 目的：提供一种用于制造具有金属栅极图案的半导体器件的方法，以能够通过使用选择性氧化处理来固化损伤。 构成：在具有栅极绝缘层的硅基板上沉积包含金属膜的金属栅极物质（S10）。 通过蚀刻金属栅极物质形成金属栅极图案（S20）。 在金属栅极图案上形成覆盖层（S30）。 在选择性地氧化含硅物质的同时进行选择性氧化处理，同时抑制用于固化金属栅极图案的损伤的金属膜的氧化（S40）。

公开(公告)号：KR1020020075000A

公开(公告)日：2002-10-04

申请号：KR1020010015150

申请日：2001-03-23

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  조만호 ,  최철준 ,  허성준

IPC: H01L21/336

CPC classification number: H01L29/4941 ,  H01L21/28088 ,  H01L21/32105 ,  H01L21/823437

Abstract: PURPOSE: A metal gate formation method of semiconductor devices is provided to minimize an oxidation of a metal electrode without affecting an oxidation of silicon by using gases contained nitrogen atoms in a selective oxidation processing. CONSTITUTION: A gate oxide(120) is formed on a semiconductor substrate. A polysilicon layer(140), a barrier metal film(150), a metal film(160) and a gate capping layer(180) are sequentially formed on the gate oxide. A metal gate pattern(200) is then formed by sequentially etching the stacked films. A selective oxidation processing is performed so as to minimize an oxidation of the metal films(150,160) and to form an oxide layer on the exposed surface of the semiconductor substrate. At this time, gases contained nitrogen atoms together with oxygen and hydrogen gases are used as the selective oxidation gas.

Abstract translation: 目的：提供半导体器件的金属栅极形成方法，以通过在选择性氧化处理中使用含有氮原子的气体来最小化金属电极的氧化而不影响硅的氧化。 构成：在半导体衬底上形成栅极氧化物（120）。 在栅极氧化物上依次形成多晶硅层（140），阻挡金属膜（150），金属膜（160）和栅极覆盖层（180）。 然后通过依次蚀刻堆叠的膜形成金属栅极图案（200）。 进行选择性氧化处理以最小化金属膜（150,160）的氧化并在半导体衬底的暴露表面上形成氧化物层。 此时，气体与氧一起含有氮原子，氢气用作选择性氧化气体。

公开(公告)号：KR1020160071769A

公开(公告)日：2016-06-22

申请号：KR1020140179331

申请日：2014-12-12

Applicant: 삼성전자주식회사

Inventor： 허성준 ,  김동욱 ,  신동학

IPC: G11C29/04 ,  G11C29/02 ,  G11C29/08 ,  G11C29/44 ,  G11C11/4078

CPC classification number: G11C29/38 ,  G11C11/401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/04 ,  G11C11/4078 ,  G11C29/02 ,  G11C29/08 ,  G11C2029/4402

Abstract: 반도체메모리장치는메모리셀 어레이및 데이터제어회로를포함한다. 상기데이터제어회로는테스트모드에서상기메모리셀 어레이의복수의메모리셀 로우들각각으로부터제1 단위씩의데이터를순차적으로독출하고, 상기제1 단위들의상응하는입력비트들을순차적으로비교하여, 상기제1 단위들을포함하는제2 단위의데이터의동일성여부를나타내는병합된테스트결과데이터를출력할수 있다.

Abstract translation: 半导体存储器件包括存储单元阵列和数据控制电路。 数据控制电路以测试模式顺序地从存储单元阵列的多个存储单元行中的每一个存储单元行中读取第一单元的数据，并且顺序地将与第一单元相对应的输入位进行比较，以输出合并的测试结果数据， 包括第一单元的第二单元是相同的。 因此，可以大大降低用于测试半导体存储器件的测试时间。

公开(公告)号：KR100441681B1

公开(公告)日：2004-07-27

申请号：KR1020010012600

申请日：2001-03-12

Applicant: 삼성전자주식회사

Inventor： 조만호 ,  구자흠 ,  최철준 ,  조준규 ,  허성준

IPC: H01L21/336

CPC classification number: H01L21/28061 ,  H01L21/28247

Abstract: In a method of forming a metal gate electrode, an annealing process is performed in a hydrogen-containing gas ambient following a selective oxidation process. During the annealing process, a metal oxide layer formed by the selective oxidation process is removed by a reduction reaction or hydrogen atoms are contained in the metal oxide layer to suppress whisker nucleation and surface mobility.

Abstract translation: 在形成金属栅极电极的方法中，在选择性氧化工艺之后的含氢气体环境中执行退火工艺。 在退火过程中，通过选择性氧化过程形成的金属氧化物层通过还原反应被除去，或者氢原子被包含在金属氧化物层中以抑制晶须成核和表面迁移率。

公开(公告)号：KR100486248B1

公开(公告)日：2005-05-03

申请号：KR1020020039834

申请日：2002-07-09

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  이창원 ,  허성준 ,  선민철 ,  윤선필

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

Abstract: 반응챔버내에 실리콘 코팅의 발생을 방지하여 파티클의 발생을 억제하고 금속 실리사이드화를 방지하는 동시에 금속층의 산화를 방지할 수 있는 실리콘옥사이드층을 포함한 반도체소자의 제조방법이 개시된다.
그 제조방법은, 반도체기판을 증착공정이 수행될 수 있는 반응챔버내로 로딩하는 단계, 상기 반응챔버내에 저온에서 분해가 가능한 질소 원소를 포함하는 질소 분위기가스를 투입하여 상기 반응챔버내를 질소 분위기로 형성하는 단계 및 상기 반응챔버내에 실리콘 소오스가스 및 산소 소오스가스를 투입하여 상기 반도체기판상에 실리콘옥사이드층을 증착하는 단계를 포함하며, 반도체기판상에는 도전층 패턴 예를 들어, 게이트라인 패턴이 형성되며, 게이트 라인 패턴의 측벽에 실리콘옥사이드층/실리콘나이트라이드층의 이중 스페이서를 형성하는 방법이 개시된다.

公开(公告)号：KR100459725B1

公开(公告)日：2004-12-03

申请号：KR1020020057456

申请日：2002-09-19

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  이창원 ,  허성준 ,  윤선필 ,  김성만

IPC: H01L21/28

CPC classification number: H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract translation: 提供了一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化工艺期间金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 覆盖层允许使用选择性氧化工艺，该选择性氧化工艺可以是利用富H 2气氛中H 2 O和H 2两者的分压的湿式氧化工艺来氧化衬底和金属栅极图案的一部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许蚀刻损伤硅基板和金属栅极图案的边缘，同时基本保持栅极绝缘层的原始厚度和金属层的导电率。

公开(公告)号：KR1020040081971A

公开(公告)日：2004-09-23

申请号：KR1020030016593

申请日：2003-03-17

Applicant: 삼성전자주식회사

Inventor： 윤선필 ,  최시영 ,  구자흠 ,  이창원 ,  김성만 ,  허성준

IPC: H01L21/336

Abstract: PURPOSE: A gate pattern of a semiconductor device and a method for forming the same are provided to reduce RC delay while maintaining good electric properties of a polysilicon gate. CONSTITUTION: A semiconductor substrate(100) is prepared. A gate insulating layer(200) is formed on the substrate. A polysilicon pattern(300a) including a protrudent part(310) and a recess part is formed on the gate insulating layer. A metal film(400a) is filled in the recess part. A hard mask layer(500a) is formed on the polysilicon pattern. A gate pattern(600) is formed by selectively removing the hard mask layer, the metal film and the polysilicon pattern.

Abstract translation: 目的：提供半导体器件的栅极图案及其形成方法以减少RC延迟，同时保持多晶硅栅极的良好电性能。 构成：制备半导体衬底（100）。 在基板上形成栅极绝缘层（200）。 在栅极绝缘层上形成包括突起部（310）和凹部的多晶硅图案（300a）。 金属膜（400a）填充在凹部中。 在多晶硅图案上形成硬掩模层（500a）。 通过选择性地去除硬掩模层，金属膜和多晶硅图案来形成栅极图案（600）。