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公开(公告)号：KR101668097B1
公开(公告)日：2016-10-24
申请号：KR1020100022353
申请日：2010-03-12
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7834 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7848
Abstract: 전계효과트랜지스터를포함하는반도체소자및 그형성방법을제공한다. 이소자에따르면, 에피택시얼패턴이게이트패턴일측의반도체기판에형성된함몰영역을채운다. 함몰영역일측의바디부상에게이트패턴이배치된다. 바디부에인접한함몰영역의측벽은바디부를향하는뾰족한리세스들의내면들을포함하거나, 뾰족한리세스의내면및 수직한하부측벽을가질수 있다.
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公开(公告)号：KR1020110103158A
公开(公告)日：2011-09-20
申请号：KR1020100022353
申请日：2010-03-12
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7834 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/66348
Abstract: 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 형성 방법을 제공한다. 이 소자에 따르면, 에피택시얼 패턴이 게이트 패턴 일측의 반도체 기판에 형성된 함몰 영역을 채운다. 함몰 영역 일측의 바디부 상에 게이트 패턴이 배치된다. 바디부에 인접한 함몰 영역의 측벽은 바디부를 향하는 뾰족한 리세스들의 내면들을 포함하거나, 뾰족한 리세스의 내면 및 수직한 하부 측벽을 가질 수 있다.
Abstract translation: 提供了一种包括场效应晶体管的半导体器件及其形成方法。 根据该元件，外延图案填充在栅极图案的一侧上的半导体衬底中形成的凹陷区域。 栅极图案设置在凹陷区域的一侧上的主体部分上。 邻近于所述主体部分的凹陷区域的侧壁包括凹部的尖头部分的面向身体的内表面，或者可以具有一个内表面和尖凹部的垂直下侧壁。
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公开(公告)号：KR1020140018746A
公开(公告)日：2014-02-13
申请号：KR1020120085398
申请日：2012-08-03
Applicant: 삼성전자주식회사
Inventor： 허정식
IPC: H01L21/302 , H01L21/336 , H01L29/78
CPC classification number: H01L21/02068 , H01L21/02063 , H01L21/02071
Abstract: The present invention relates to a substrate treating method and an apparatus thereof. According to one embodiment of the present invention, the substrate treating method includes a step of forming a metal layer on a substrate; and a step of removing particles by processing the substrate by using a buffer solution mixed with an alkali solution and water including CO2. [Reference numerals] (100) First cleaning solution supply unit; (200) Second cleaning solution supply unit; (300) Cleaning solution mixing unit; (400) Spray unit
Abstract translation: 本发明涉及一种基板处理方法及其装置。 根据本发明的一个实施例，基板处理方法包括在基板上形成金属层的步骤; 以及通过使用与碱溶液和包含CO 2的水混合的缓冲溶液处理基板来除去颗粒的步骤。 （附图标记）（100）第一清洗液供给单元; （200）第二清洗液供应单元; （300）清洗液混合装置; （400）喷涂单元
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公开(公告)号：KR100843246B1
公开(公告)日：2008-07-02
申请号：KR1020070049960
申请日：2007-05-22
Applicant: 삼성전자주식회사
IPC: H01L21/76 , H01L21/762
CPC classification number: H01L21/76224
Abstract: A semiconductor device having an STI(Shallow Trench Isolation) structure and a manufacturing method thereof are provided to suppress generation of a recess by forming a first and second impurity doping oxide layers on exposed parts of a sidewall oxide layer and a gap-fill oxide layer. A trench is formed on an isolation region of a substrate(100) in order to define an active region. A sidewall oxide layer(130) is formed to cover an inner wall of the trench. A nitride layer liner(140) is formed on the sidewall oxide layer. A gap-fill insulating layer(150) is formed on the nitride layer liner in order to bury the trench. A first impurity doping oxide layer is formed on an edge region of both ends of the sidewall oxide layer in order to be extended from the substrate to the nitride layer liner at an entrance of the adjacent trench on the substrate.
Abstract translation: 提供具有STI（浅沟槽隔离）结构的半导体器件及其制造方法，以通过在侧壁氧化物层和间隙填充氧化物层的暴露部分上形成第一和第二杂质掺杂氧化物层来抑制凹陷的产生 。 在衬底（100）的隔离区上形成沟槽以便限定有源区。 形成侧壁氧化物层（130）以覆盖沟槽的内壁。 氮化物层衬垫（140）形成在侧壁氧化物层上。 在氮化物层衬垫上形成间隙填充绝缘层（150）以埋入沟槽。 在侧壁氧化物层的两端的边缘区域上形成第一杂质掺杂氧化物层，以在衬底上的相邻沟槽的入口处从衬底延伸到氮化物层衬垫。
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公开(公告)号：KR101576529B1
公开(公告)日：2015-12-11
申请号：KR1020100013123
申请日：2010-02-12
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/306 , H01L21/336
CPC classification number: H01L21/823807 , H01L21/30608 , H01L21/3086 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S438/938
Abstract: 본발명은반도체기판에 SiGe 혼정층및 (111) 결정면을갖는실리콘파셋트(Si facet) 캡핑층을갖는 MOS 트랜지스터를제공한다.본발명의 SiGe 혼정층상에 (111) 결정면을갖는실리콘파셋트(Si facet) 캡핑층을갖는 MOS 트랜지스터는, 반도체기판에게이트전극이형성되어있고, 상기게이트전극중 p형 MOS 트랜지스터는 SiGe 혼정층에피택셜층소오스드레인이형성되어있고, 상기 SiGe 혼정층상부는식각결정면에따라서식각율이다른식각용액을이용한습식식각으로형성된 (111) 결정면을갖는실리콘파셋트(Si facet) 캡핑층을포함하는것을특징으로한다.
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Patent Agency Ranking
公开(公告)号：KR1020130125583A
公开(公告)日：2013-11-19
申请号：KR1020120049216
申请日：2012-05-09
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/66477 , H01L29/6656 , H01L29/6659 , H01L21/0234
Abstract: The present invention provides a semiconductor device and a method manufacturing the same. The semiconductor device includes a first insulator film arranged on a substrate; a gate electrode arranged on the first insulator film; and a second insulator film including a first discharge site and arranged on the gate electrode and the first insulator film.
Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括布置在衬底上的第一绝缘膜; 布置在所述第一绝缘膜上的栅电极; 以及包括第一放电位置并且布置在栅电极和第一绝缘膜上的第二绝缘膜。
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公开(公告)号：KR101918639B1
公开(公告)日：2018-11-15
申请号：KR1020120000586
申请日：2012-01-03
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L21/02068 , H01L21/28088 , H01L21/28123 , H01L21/28518 , H01L21/32134 , H01L21/76224 , H01L21/76814 , H01L21/823418 , H01L21/823443 , H01L21/823456 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66651
Abstract: 반도체장치를형성하는방법이개시된다. 상기방법은실리콘기판상에게이트절연막을형성하고, 상기게이트절연막상에금속질화막을포함하는게이트를형성하고, 상기게이트양측의상기실리콘기판에소스드레인을형성하고, 상기게이트의측벽에측벽스페이서를형성하고, 그리고상기소스드레인상에금속실리사이드막을형성하는것을포함한다. 상기금속실리사이드막을형성하는것은금속을상기소스드레인상에제공하고, 열처리공정을수행하여상기금속과실리콘을반응시키고, 그리고전기분해된황산을사용하여미반응된상기금속의잔류물을제거하는것을포함한다.
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公开(公告)号：KR101908288B1
公开(公告)日：2018-10-16
申请号：KR1020120049216
申请日：2012-05-09
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/66477 , H01L29/6656 , H01L29/6659
Abstract: 반도체소자및 이를제조하는방법을제공한다. 반도체소자는, 기판상에배치되는제1 절연막, 제1 절연막상에배치되는게이트전극및 게이트전극및 제1 절연막상에배치되며, 제1 방전사이트(discharge site)를포함하는제2 절연막을포함한다.
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公开(公告)号：KR1020130079848A
公开(公告)日：2013-07-11
申请号：KR1020120000586
申请日：2012-01-03
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L21/02068 , H01L21/28088 , H01L21/28123 , H01L21/28518 , H01L21/32134 , H01L21/76224 , H01L21/76814 , H01L21/823418 , H01L21/823443 , H01L21/823456 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66651
Abstract: PURPOSE: A semiconductor device and a forming method thereof are provided to improve an operation speed of a high integrated transistor by using a gate with metal to reduce the resistance of a gate. CONSTITUTION: A gate insulation layer (31) is formed on a silicon substrate (10). A gate including a metal nitride layer (33) is formed on the gate insulation layer. A source and a drain are formed on the silicon substrate of both sides of the gate. A sidewall spacer (37) is formed on the sidewall of the gate. A metal silicide layer (53) is formed on the source and the drain.
Abstract translation: 目的：提供半导体器件及其形成方法，以通过使用具有金属的栅极来提高高集成晶体管的操作速度，以降低栅极的电阻。 构成：在硅衬底（10）上形成栅绝缘层（31）。 在栅极绝缘层上形成包括金属氮化物层（33）的栅极。 源极和漏极形成在栅极两侧的硅衬底上。 侧壁间隔件（37）形成在门的侧壁上。 在源极和漏极上形成金属硅化物层（53）。
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公开(公告)号：KR1020110093217A
公开(公告)日：2011-08-18
申请号：KR1020100013123
申请日：2010-02-12
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/306 , H01L21/336
CPC classification number: H01L21/823807 , H01L21/30608 , H01L21/3086 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S438/938 , H01L21/67075
Abstract: PURPOSE: A semiconductor device with a silicon palette using wet etching and a manufacturing method thereof are provided to minimize thermal damage using an epitaxial process at a low temperature. CONSTITUTION: An SiGe(Silicon-Germanium) mixed layer trench is formed on a semiconductor substrate(200). A SiGe mixed layer(245) is formed in the trench using an epitaxial process. A silicon layer is grown on the SiGe mixed layer by a single Si material through an epitaxial process. A silicon facet(260) has an inclined surface by wet etching. The wet etching uses etchant which has a different etching rate according to an etching surface.
Abstract translation: 目的：提供使用湿式蚀刻的具有硅调色板的半导体器件及其制造方法，以在低温下使用外延工艺来最小化热损伤。 构成：在半导体衬底（200）上形成SiGe（硅 - 锗）混合层沟槽。 使用外延工艺在沟槽中形成SiGe混合层（245）。 通过外延工艺通过单个Si材料在SiGe混合层上生长硅层。 硅刻面（260）通过湿蚀刻具有倾斜表面。 湿式蚀刻使用根据蚀刻表面具有不同蚀刻速率的蚀刻剂。
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