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公开(公告)号：KR101813174B1
公开(公告)日：2017-12-29
申请号：KR1020100096522
申请日：2010-10-04
Applicant: 삼성전자주식회사
IPC: H01L29/778
Abstract: 게이트에의해둘러싸인 HEMT에관해개시되어있다. 본발명의일 실시예에의한 HEMT는 2DEG를포함하는채널층, 상기채널층에상기 2DEG를유발시키는분극층및 상기분극층상에형성된소스, 드레인및 게이트를포함하고, 상기게이트는상기드레인을완전히둘러싼다. 상기게이트는원형또는비원형으로드레인을둘러쌀수 있다.
Abstract translation: Gt; HEMT被门包围。 栅极上的本发明的实施例的HEMT包括偏振层和一个源极，漏极，和形成包括2DEG沟道层的偏振层上的栅极，从而使2DEG在沟道层，和具有漏极 完全封闭。 栅极可以以圆形或非圆形包围漏极。
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公开(公告)号：KR101680767B1
公开(公告)日：2016-11-30
申请号：KR1020100097417
申请日：2010-10-06
Applicant: 삼성전자주식회사 , 경북대학교 산학협력단
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/66462 , H01L21/0254 , H01L21/76237 , H01L29/0847 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/4236 , H01L29/7787
Abstract: 불순물주입을이용한고출력의고 전자이동도트랜지스터(HEMT) 제조방법에관해개시되어있다. 일실시예에의한개시된 HEMT의제조방법은기판상에제1 물질층을형성하고, 상기제1 물질층의전기적저항을높인다음, 이러한제1 물질층상에제1 물질층보다밴드갭이큰, 이격된소스패턴과드레인패턴을형성하는과정을포함한다.
Abstract translation: 所述方法可以包括在衬底上形成第一材料层，增加第一材料层的电阻，以及在第一材料层上形成彼此间隔开的源图案和漏极图案，带隙为 源极和漏极图案大于第一材料层的带隙。
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公开(公告)号：KR101356694B1
公开(公告)日：2014-01-29
申请号：KR1020070045509
申请日：2007-05-10
Applicant: 삼성전자주식회사
CPC classification number: H01L33/18
Abstract: 실리콘 나노와이어를 발광소자로서 이용하는 발광 다이오드 및 그 제조 방법을 개시한다. 본 발명의 한 유형에 따른 발광 다이오드는, 반도체 기판; 상기 반도체 기판의 상면에서 서로 마주하도록 배치된 제 1 및 제 2 반도체 돌출부; 상기 제 1 및 제 2 반도체 돌출부 사이에 현가된 반도체 나노와이어; 및 상기 제 1 및 제 2 반도체 돌출부의 상면에 각각 형성된 제 1 및 제 2 전극;을 포함하는 것을 특징으로 한다.
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公开(公告)号：KR1020120125041A
公开(公告)日：2012-11-14
申请号：KR1020110043082
申请日：2011-05-06
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/432 , H01L29/66462
Abstract: PURPOSE: A high electron mobility transistor and a manufacturing method thereof are provided to strengthen threshold voltage performance by controlling the depth of a recess region formed on a channel supply layer. CONSTITUTION: A channel layer(C1) comprises 2DEG(2 Dimensional Electron Gas). A channel supply layer(CS1) comprises an etching stopping layer and a top layer. The channel supply layer has a recess region(R1). A gate electrode comprises the recess region of the channel supply layer. A source electrode and a drain electrode are included on both sides of the gate electrode. A bottom layer is formed between the channel supply layer and the etching stopping layer.
Abstract translation: 目的：提供高电子迁移率晶体管及其制造方法，以通过控制形成在沟道供应层上的凹陷区域的深度来增强阈值电压性能。 构成：通道层（C1）包括2DEG（2维电子气体）。 沟道供给层（CS1）包括蚀刻停止层和顶层。 通道供给层具有凹部（R1）。 栅电极包括沟道供应层的凹陷区域。 源电极和漏极包括在栅电极的两侧。 在沟道供给层和蚀刻停止层之间形成底层。
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公开(公告)号：KR1020120010512A
公开(公告)日：2012-02-03
申请号：KR1020100072098
申请日：2010-07-26
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
Abstract: PURPOSE: A high electron mobility transistor having multi channel and a method of manufacturing the same are provided to increase insulation breakdown voltage by preventing the concentration of electric field on a gate. CONSTITUTION: A lamination structure(20) is arranged in a substrate(30). The lamination structure comprises a plurality of the material layer(40A,40B). First to third holes(h1,h2,h3) are formed in the lamination structure. A source electrode(52S) and a drain electrode(52D) cover both ends of an Y-axis of the lamination structure. A gate(54G) is arranged in the lamination structure between the drain electrode and the source electrode.
Abstract translation: 目的：提供具有多通道的高电子迁移率晶体管及其制造方法，以通过防止栅极上的电场集中来提高绝缘击穿电压。 构成：层叠结构（20）布置在衬底（30）中。 层压结构包括多个材料层（40A，40B）。 在层压结构中形成第一至第三孔（h1，h2，h3）。 源电极（52S）和漏电极（52D）覆盖层叠结构的Y轴的两端。 栅极（54G）布置在漏电极和源电极之间的层叠结构中。
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Patent Agency Ranking
公开(公告)号：KR1020110136719A
公开(公告)日：2011-12-21
申请号：KR1020110056439
申请日：2011-06-10
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/778 , H01L29/0847 , H01L29/1029 , H01L29/1066 , H01L29/2003 , H01L29/267 , H01L29/4236 , H01L29/42364 , H01L29/517 , H01L29/66431 , H01L29/66462 , H01L29/7785 , H01L29/7786
Abstract: PURPOSE: A high electron mobility transistor and a manufacturing method thereof are provided to improve the reproducibility of an LCD area by controlling the electron concentration of the LCD area through the thickness adjustment of a thin film. CONSTITUTION: A buffer layer(24) is formed on a substrate(20). A first material layer(30) is formed on the buffer layer. A second material layer(32) is formed on the first material layer. A negative charge(31) is formed in the interface of the first material layer which is contacted with the second material layer. A channel increase layer is formed on the second material layer.
Abstract translation: 目的：提供高电子迁移率晶体管及其制造方法，以通过薄膜的厚度调整来控制LCD面积的电子浓度来提高LCD面积的再现性。 构成：在衬底（20）上形成缓冲层（24）。 第一材料层（30）形成在缓冲层上。 第二材料层（32）形成在第一材料层上。 在与第二材料层接触的第一材料层的界面中形成负电荷（31）。 在第二材料层上形成通道增加层。
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公开(公告)号：KR1020110122525A
公开(公告)日：2011-11-10
申请号：KR1020100042083
申请日：2010-05-04
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L29/778
CPC classification number: H01L29/778 , H01L21/28008 , H01L29/1029 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42364 , H01L29/66431 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L29/78621
Abstract: PURPOSE: A high electron mobility transistor with a LDD(Lightly Doped Drain) area and a manufacturing method thereof are provided to prevent the concentration of a 2DEG(2-Dimensional Electron Gas) channel from being drastically changed according to the etched thickness of a channel supplying layer by utilizing an etch buffer layer as an etch stopping layer for forming an LDD area on the 2DEG channel. CONSTITUTION: A buffer layer(12) is formed on a substrate(10). First and second material layers(30,32) are successively formed on the buffer layer. The second material layer and a third material layer(34) are successively formed on the first material layer. The 2DEG(2-Dimensional Electron Gas) of an LDD(Lightly Doped Drain) area(A1) becomes generated by the second material layer. A gate(36) is formed on the second material layer which corresponds to the LDD area.
Abstract translation: 目的：提供具有LDD（轻掺杂漏极）面积的高电子迁移率晶体管及其制造方法，以防止2DEG（2维电子气体）通道的浓度根据通道的蚀刻厚度而急剧变化 通过利用蚀刻缓冲层作为用于在2DEG通道上形成LDD区域的蚀刻停止层来提供层。 构成：在衬底（10）上形成缓冲层（12）。 第一和第二材料层（30,32）依次形成在缓冲层上。 第二材料层和第三材料层（34）依次形成在第一材料层上。 LDD（轻掺杂漏极）区域（A1）的2DEG（二维电子气体）由第二材料层产生。 在对应于LDD区域的第二材料层上形成栅极（36）。
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公开(公告)号：KR1020110103740A
公开(公告)日：2011-09-21
申请号：KR1020100022948
申请日：2010-03-15
Applicant: 삼성전자주식회사
IPC: H03K17/30 , H03K17/687
CPC classification number: H03K17/6871 , H02M1/08 , H02M3/158 , H02M3/337 , H02M2001/0074 , H03K2217/0081
Abstract: 본 발명은 반도체 장치에 관한 것으로, 음의 문턱 전압(threshold voltage)을 가지는 스위칭 소자, 및 전원 단자와 접지 단자 사이에 연결되어, 스위칭 소자를 구동하기 위한 구동 전압을 제공하는 구동부를 포함하고, 스위칭 소자는, 접지 단자에서 공급되는 접지 전압보다 높은 가상 접지 전압을 가지는 가상 접지 노드(node)에 연결되어, 구동 전압과 가상 접지 전압의 차이가 상기 문턱 전압보다 큰 경우에 온(on)된다.
Abstract translation: 本发明涉及一种半导体器件，连接在开关元件之间，并且一个电源端子与所述接地端子具有的声音的阈值电压（阈值电压），其包括一个驱动部分，其用于驱动所述开关元件提供驱动电压，所述开关 元件连接到具有比待从接地端子供给的接地电压高的虚拟接地电压的虚拟接地节点（节点），并且驱动电压并且在虚拟接地（上），如果大于阈值电压更大的电压之间的差。
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公开(公告)号：KR1020110033747A
公开(公告)日：2011-03-31
申请号：KR1020090091360
申请日：2009-09-25
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: G11C11/22 , G11C11/223 , H01L21/28291 , H01L27/11597 , H01L27/1203 , H01L29/1606 , H01L29/78391
Abstract: PURPOSE: Ferroelectric memory devices and an operating method of the same are provided to increase extensibility by forming a ferroelectric layer to reduce the interface between ferroelectric cells. CONSTITUTION: In a ferroelectric memory devices and an operating method of the same, a unit area includes a channel(20), a ferroelectric layer(30), and a gate electrode(40). The ferroelectric layer is interposed between the channel and the gate electrode. The channel is formed along a bit line direction. The gate electrode is formed along a word line direction. The channel and the gate electrode are crossed with each other at a plurality of areas.
Abstract translation: 目的：提供铁电存储器件及其操作方法，以通过形成铁电层以减小铁电单元之间的界面来增加延展性。 构成：在铁电存储器件及其操作方法中，单位区域包括沟道（20），铁电层（30）和栅电极（40）。 铁电层介于通道和栅电极之间。 通道沿着位线方向形成。 栅电极沿着字线方向形成。 通道和栅电极在多个区域彼此交叉。
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公开(公告)号：KR1020110032845A
公开(公告)日：2011-03-30
申请号：KR1020090090561
申请日：2009-09-24
Applicant: 삼성전자주식회사
IPC: H01L29/778
CPC classification number: H01L29/207 , H01L29/2003 , H01L29/66462 , H01L29/7787
Abstract: PURPOSE: A power electronic device and a method of manufacturing the same are provided to increase productivity by removing an additional material layer for making the certain area of 2DEG channel open and simplifying a process step. CONSTITUTION: In a power electronic device and a method of manufacturing the same, a lower semiconductor layer and upper semiconductor layer are successively laminated in a substrate(10). A gate(40), a source(50), and a drain(60) are separated on the semiconductor layer. A 2DEG channel is formed in the interface of the upper and lower semiconductor layers. The gate is located on the top side of the upper semiconductor layer. A buffer layer(15) is interposed between the substrate and the lower semiconductor layer.
Abstract translation: 目的：提供一种电力电子设备及其制造方法，以通过去除用于使2DEG通道的特定区域打开并简化处理步骤的附加材料层来提高生产率。 构成：在功率电子器件及其制造方法中，下半导体层和上半导体层依次层叠在基板（10）中。 在半导体层上分离栅极（40），源极（50）和漏极（60）。 在上半导体层和下半导体层的界面中形成2DEG沟道。 栅极位于上半导体层的顶侧。 在衬底和下半导体层之间插入缓冲层（15）。
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