公开(公告)号：KR1020080071819A

公开(公告)日：2008-08-05

申请号：KR1020070010156

申请日：2007-01-31

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 김수환 ,  최창준

IPC: H03K19/00

CPC classification number: H03K17/007 ,  G06F1/26 ,  H03K17/163 ,  H03K17/22 ,  H03K17/284 ,  H03K19/0016

Abstract: A semiconductor integrated circuit device and a power control method are provided to prevent a noise due to an abrupt change of current by increasing gradually external power applied to a logic block. A semiconductor integrated circuit device includes a logic block(200) and a voltage control circuit for controlling an operational voltage applied to the logic block. The voltage control circuit controls the operational voltage in order to increase gradually the operational voltage at an initial operation of the logic block. The voltage control circuit includes a power gate circuit(110) for supplying the operational voltage to the logic block and a control unit for controlling the power gate circuit in response to the operational voltage and an external command. The control unit controls the power gate circuit in order to increase gradually the operational voltage.

Abstract translation: 提供半导体集成电路器件和功率控制方法，以通过逐渐增加施加到逻辑块的外部功率来防止由于电流突然变化引起的噪声。 半导体集成电路器件包括逻辑块（200）和用于控制施加到逻辑块的工作电压的电压控制电路。 电压控制电路控制操作电压，以便在逻辑块的初始操作期间逐渐增加操作电压。 电压控制电路包括用于向逻辑块提供工作电压的电源门电路（110）和用于响应于工作电压和外部命令控制电源门电路的控制单元。 控制单元控制电源门电路，以便逐渐增加工作电压。

公开(公告)号：KR101348170B1

公开(公告)日：2014-01-09

申请号：KR1020070010156

申请日：2007-01-31

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 김수환 ,  최창준

IPC: H03K19/00

CPC classification number: H03K17/007 ,  G06F1/26 ,  H03K17/163 ,  H03K17/22 ,  H03K17/284 ,  H03K19/0016

Abstract: 여기에 제공되는 반도체 집적 회로 장치는 논리 블록과; 그리고 상기 논리 블록으로 공급되는 동작 전압을 제어하는 전압 제어 회로를 포함하며, 상기 전압 제어 회로는 상기 논리 블록의 초기 동작시 단계적으로 증가되도록 상기 동작 전압을 제어한다.

公开(公告)号：KR1020050006835A

公开(公告)日：2005-01-17

申请号：KR1020030046801

申请日：2003-07-10

Applicant: 삼성전자주식회사

Inventor： 최창준

IPC: G11C7/06

CPC classification number: G11C7/08 ,  G11C7/065 ,  G11C7/1048

Abstract: PURPOSE: A BUS driver by using a sense amplifier is provided to realize the circuit not generating the glitch due to the signal delay between the selection signal and the data by driving the BUS using the sense amplifier. CONSTITUTION: A BUS driver by using a sense amplifier includes a precharge circuit(10), a sense amplifier(20) and a driving circuit(40). The precharge circuit precharge the BUS. The sense amplifier amplifies the data to be loaded to the BUS. And, the driving circuit drives the BUS by using the output signal of the sense amplifier.

Abstract translation: 目的：通过使用读出放大器提供BUS驱动器，以通过使用读出放大器驱动总线来实现由于选择信号和数据之间的信号延迟而不产生毛刺的电路。 构成：通过使用读出放大器的BUS驱动器包括预充电电路（10），读出放大器（20）和驱动电路（40）。 预充电电路为BUS充电。 读出放大器放大要加载到总线的数据。 并且，驱动电路通过使用读出放大器的输出信号驱动BUS。

公开(公告)号：KR1020100020896A

公开(公告)日：2010-02-23

申请号：KR1020090043352

申请日：2009-05-19

Applicant: 삼성전자주식회사

Inventor： 박성배 ,  정건옥 ,  신영민 ,  이회진 ,  최창준 ,  김민수

IPC: H03K17/693

CPC classification number: H03K17/693 ,  H03K17/005 ,  H03K19/0013 ,  H03K19/1737 ,  H03K2217/0036

Abstract: PURPOSE: A fast multiplexer, a semiconductor device including the same, and an electronic device including the semiconductor device are provided to process data with low power and high speed using separated data pathes. CONSTITUTION: A first path circuit(13) transmits one of a plurality of input signals as a first transmission signal using a plurality of first type pass transistors. A second path circuit(15) transmits one of the plurality of input signals as a second transmission signal using a plurality of second type pass transistors. An output circuit(17) outputs one of two voltages as an output signal in response to the first and second transmission signals. The first and second type pass transistors are respectively comprised of NMOSFET or PMOSFET.

Abstract translation: 目的：提供一种快速多路复用器，包括该半导体器件的半导体器件和包括该半导体器件的电子器件，以使用分离的数据裸片来处理低功率和高速度的数据。 构成：第一路径电路（13）使用多个第一类型的通过晶体管将多个输入信号中的一个作为第一发送信号发送。 第二路径电路（15）使用多个第二类型的通过晶体管将多个输入信号中的一个作为第二发送信号发送。 输出电路（17）响应于第一和第二传输信号而输出两个电压中的一个作为输出信号。 第一和第二类型传输晶体管分别由NMOSFET或PMOSFET组成。

公开(公告)号：KR1020020031519A

公开(公告)日：2002-05-02

申请号：KR1020000062016

申请日：2000-10-20

Applicant: 삼성전자주식회사

Inventor： 최창준

IPC: H03K19/0944

CPC classification number: H03K19/1738 ,  H03K19/0948

Abstract: PURPOSE: An improved push-pull cascode logic circuit is provided to improve an operating speed thereof by setting a threshold voltage of NMOS transistors of a binary tree section lower than that of NMOS transistors of a cross-couple latch. CONSTITUTION: A cross-couple latch(100) is connected to a supply voltage. The cross-couple latch(100) includes PMOS transistors(MP10,MP12) and NMOS transistors(MN10,MN12). A binary tree section(200) is connected to the supply voltage, a ground voltage, and output terminals(N1,N2) of the cross-couple latch(100). The binary tree section(200) includes a plurality of NMOS transistors(MN14-MN24). Each of the NMOS transistors(MN14-MN24) has a threshold voltage lower than that of each of the PMOS transistors(MP10,MP12) and NMOS transistors(MN10,MN12) of the cross-couple latch(100).

Abstract translation: 目的：提供改进的推挽共源共栅逻辑电路，通过将二叉树段的NMOS晶体管的阈值电压设置为低于交叉耦合锁存器的NMOS晶体管的阈值电压来提高其工作速度。 构成：交叉耦合锁存器（100）连接到电源电压。 交叉耦合锁存器（100）包括PMOS晶体管（MP10，MP12）和NMOS晶体管（MN10，MN12）。 二叉树部分（200）连接到交叉耦合锁存器（100）的电源电压，地电压和输出端子（N1，N2）。 二叉树部分（200）包括多个NMOS晶体管（MN14-MN24）。 每个NMOS晶体管（MN14-MN24）的阈值电压低于交叉耦合锁存器（100）的PMOS晶体管（MP10，MP12）和NMOS晶体管（MN10，MN12）中的每一个的阈值电压。

公开(公告)号：KR101316788B1

公开(公告)日：2013-10-11

申请号：KR1020070002112

申请日：2007-01-08

Applicant: 삼성전자주식회사

Inventor： 최창준 ,  김수환

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: 여기에 제공되는 반도체 집적 회로 장치는 논리 블록과 그리고 상기 논리 블록으로 공급되는 전력을 제어하는 전력 제어 회로를 포함하며, 상기 전력 제어 회로는 데이터 유지 모드시 상기 논리 블록에 저장된 데이터를 유지하는 데 필요한 최소의 동작 전압을 공급하도록 구성된다.

Abstract translation: 在此提供的半导体集成电路器件包括逻辑块和用于控制提供给逻辑块的功率的功率控制电路，其中功率控制电路被配置为将存储在逻辑块中的数据保持在数据保持模式 并配置为提供最低工作电压。

公开(公告)号：KR100459735B1

公开(公告)日：2004-12-03

申请号：KR1020030011210

申请日：2003-02-22

Applicant: 삼성전자주식회사

Inventor： 최창준

IPC: G06F7/50

CPC classification number: G06F7/507 ,  G06F7/503 ,  G06F7/508

Abstract: A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.

Abstract translation: 进位先行加法器可以包括：进位产生电路，用于基于N位加数和被加数产生进位传播比特值并且携带用于M块的取消比特值; 块携带电路，用于基于比特值产生块携带信号; 曼彻斯特进位链配置比特进位电路，用于基于比特值产生其中在M个块中的每一个中存在块进位的第一比特进位信号和不存在块进位的第二进位比特信号; 控制电路，用于与逻辑电平的时钟使能信号无关地生成基于块进位信号的选择控制信号; 以及求和选择电路，用于在第一位进位信号和第二位进位信号之间进行选择，并将进位传送位值和所选进位信号相加。

公开(公告)号：KR1020030053594A

公开(公告)日：2003-07-02

申请号：KR1020010083347

申请日：2001-12-22

Applicant: 삼성전자주식회사

Inventor： 최창준

IPC: G11C7/00

Abstract: PURPOSE: A method and a circuit for outputting data capable of reducing a coupling effect are provided to reduce the coupling effect on an output node by discharging a precharge voltage in a predetermined level. CONSTITUTION: A flip-flop(100) comprises a plurality of transistors, a plurality of inverters, and a pull-down circuit(110). An inverter(1) inverts an external clock signal(GCLK). An inverter(3) generates an internal clock signal(CLK) delaying and inverting an output signal from the inverter(1) for a predetermined time. The output signal from the inverter(1) is inputted to gates of transistors(P19,P21). The transistor(P19) is connected between a node(ND13) and a ground power source. The transistor(P21) is connected between a node(ND15) and the ground power source. The internal clock signal(CLK) is inputted to gates of transistors(P11,P13,N23). The transistor(P11) is connected between a power voltage(VDD) and the node(ND13). The transistor(P13) is connected between the power voltage(VDD) and the node(ND15).

Abstract translation: 目的：提供一种用于输出能够减小耦合效应的数据的方法和电路，以通过将预充电电压放电到预定电平来减小对输出节点的耦合效应。 构成：触发器（100）包括多个晶体管，多个反相器和下拉电路（110）。 反相器（1）反相外部时钟信号（GCLK）。 逆变器（3）产生将来自逆变器（1）的输出信号延迟并反相预定时间的内部时钟信号（CLK）。 来自反相器（1）的输出信号被输入到晶体管（P19，P21）的栅极。 晶体管（P19）连接在节点（ND13）和接地电源之间。 晶体管（P21）连接在节点（ND15）和地电源之间。 内部时钟信号（CLK）被输入到晶体管（P11，P13，N23）的栅极。 晶体管（P11）连接在电源电压（VDD）和节点（ND13）之间。 晶体管（P13）连接在电源电压（VDD）和节点（ND15）之间。

公开(公告)号：KR1020000008016A

公开(公告)日：2000-02-07

申请号：KR1019980027659

申请日：1998-07-09

Applicant: 삼성전자주식회사

Inventor： 최창준 ,  김광일

IPC: H01L27/06

CPC classification number: H01L2924/19104

Abstract: PURPOSE: A semiconductor device is provided to compensate fluctuation or reduction of power supply voltage by forming a decoupling capacitor on a chip surface. CONSTITUTION: The device comprises a semiconductor chip; a plurality of pads arranged at an outside of the semiconductor chip to apply an external electric signal to an inside thereof; a plurality of a first and a second power lines alternatively arranged in the inside thereof, wherein each of the first and the second power lines is a path where a first and a second constant voltages are supplied; and at least one capacitor arranged on the semiconductor chip between a first and a second power lines.

Abstract translation: 目的：提供半导体器件，通过在芯片表面形成去耦电容来补偿电源电压的波动或降低。 构成：该装置包括半导体芯片; 布置在半导体芯片的外部的多个焊盘，以向其内部施加外部电信号; 多个交替布置在其内部的第一和第二电力线，其中第一和第二电力线中的每一个是提供第一和第二恒定电压的路径; 以及布置在第一和第二电力线之间的半导体芯片上的至少一个电容器。

公开(公告)号：KR1020050017766A

公开(公告)日：2005-02-23

申请号：KR1020030055076

申请日：2003-08-08

Applicant: 삼성전자주식회사

Inventor： 최창준

IPC: G06F13/40

CPC classification number: H03K17/693

Abstract: PURPOSE: A multi-bus driving device for driving multiple buses on a microprocessor operated at high-speed is provided to enhance areal efficiency by driving the multiple buses with one code extender using a bus selection circuit and drive the buses faster by driving the buses with a PMOS(Positive Metal Oxide Semiconductor)/NMOS transistor pair. CONSTITUTION: A control logic(206) generates/outputs control signals and bus selection signals. A byte rotator(202) divides data from a data source into a byte unit and changes order of the divided data according to byte operation. The code expender(204) outputs the data selected by the byte operation among the data inputted from the byte rotator by responding to the control signals, extends the unselected data to a predetermined code value, and output it. The bus selection circuit(208) selects the bus among the multiple buses by responding to the bus selection signals and loads the data inputted from the code extender on the selected bus.

Abstract translation: 目的：提供一种用于在高速运行的微处理器上驱动多个总线的多总线驱动装置，以通过使用总线选择电路驱动多个总线，通过一个代码扩展器来驱动多个总线，并通过驱动总线更快地驱动总线 PMOS（正金属氧化物半导体）/ NMOS晶体管对。 构成：控制逻辑（206）产生/输出控制信号和总线选择信号。 字节旋转器（202）将来自数据源的数据分割成字节单元，并根据字节操作改变分割数据的顺序。 代码延伸器（204）通过响应于控制信号输出从字节旋转器输入的数据中通过字节操作选择的数据，将未选择的数据扩展到预定的代码值，并将其输出。 总线选择电路（208）通过响应总线选择信号来选择多个总线中的总线，并将从代码扩展器输入的数据加载到所选择的总线上。