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    최소화된 상부전극의 컨택을 갖는 저항성 메모리 소자 및 그 제조방법
    3.
    发明公开
    최소화된 상부전극의 컨택을 갖는 저항성 메모리 소자 및 그 제조방법 无效
    具有最小电极接触的RRAM器件及其制造方法

    公开(公告)号：KR1020120012049A

    公开(公告)日：2012-02-09

    申请号：KR1020100073919

    申请日：2010-07-30

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  유경창 ,  오정훈

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L43/08 ,  G11C13/0004 ,  H01L27/222 ,  H01L43/12

    Abstract: PURPOSE: A resistive memory device with a minimized upper electrode contact and a manufacturing method thereof are provided to arrange an upper electrode with a sidewall electrode and a sidewall contact part, thereby maximally reducing area touched with a resistance variable material layer. CONSTITUTION: A resistance variable layer(30) is arranged between a lower electrode(20) and an upper electrode(70). The upper electrode is formed along one side surface of a first insulating film. The first insulating film is arranged on one side of the upper part of the resistance variable layer. The upper electrode is comprised of a sidewall contact part(56) and a sidewall electrode(52) arranged on one lateral surface of the first insulating film. The sidewall contact part is arranged on the upper part of the first insulating film in order to be connected to the sidewall electrode.

    Abstract translation: 目的：提供具有最小化的上电极接触的电阻式存储器件及其制造方法，以使具有侧壁电极和侧壁接触部分的上电极布置，从而最大限度地减少用电阻可变材料层触摸的面积。 构成：电阻变化层（30）设置在下电极（20）和上电极（70）之间。 上电极沿着第一绝缘膜的一个侧面形成。 第一绝缘膜布置在电阻变化层的上部的一侧。 上电极由布置在第一绝缘膜的一个侧表面上的侧壁接触部分（56）和侧壁电极（52）组成。 侧壁接触部分布置在第一绝缘膜的上部，以便连接到侧壁电极。

    반도체 소자 및 그 구동 방법
    5.
    发明公开
    반도체 소자 및 그 구동 방법 有权
    半导体器件及其驱动方法

    公开(公告)号：KR1020110081623A

    公开(公告)日：2011-07-14

    申请号：KR1020100001878

    申请日：2010-01-08

    Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

    Inventor： 오정훈 ,  유경창 ,  박병국 ,  오경석 ,  백인규

    IPC: G11C16/00 ,  G11C16/30 ,  G11C11/21

    CPC classification number: G11C13/0002 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/102 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

    Abstract: PURPOSE: A semiconductor devices and a method of driving the same are provided to implement high integration by preventing the interference between nonvolatile memory cells. CONSTITUTION: In a semiconductor devices and a method of driving the same, a unit cell structure(1) comprises electrode layers(M1,M2), a bipolar resistance memory material film(RM1), and a unipolar resistance memory material film(RM2) The bipolar resistance memory material film and the unipolar resistance memory material film are formed between electrode layers which are opposite to each other. The bipolar resistance memory material film and the unipolar resistance memory material film are electrically serially connected. The electrode layers include resistance memory material films which are connected to conductive lines respectively.

    Abstract translation: 目的：提供半导体器件及其驱动方法，以通过防止非易失性存储单元之间的干扰来实现高集成度。 构成：在半导体器件及其驱动方法中，单元电池结构（1）包括电极层（M1，M2），双极性电阻记忆材料膜（RM1）和单极电阻存储材料膜（RM2） 双极性电阻记忆材料膜和单极电阻记忆材料膜形成在彼此相对的电极层之间。 双极性电阻记忆材料膜和单极性电阻记忆材料膜电连接。 电极层包括分别连接到导线的电阻记忆材料膜。

    스페이서 구조를 갖는 저항성 메모리 소자 및 그 제조방법
    7.
    发明公开
    스페이서 구조를 갖는 저항성 메모리 소자 및 그 제조방법 有权
    具有间隔结构的RRAM装置及其制造方法

    公开(公告)号：KR1020110136644A

    公开(公告)日：2011-12-21

    申请号：KR1020100056781

    申请日：2010-06-15

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  유경창 ,  오정훈

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L45/04 ,  H01L21/31051 ,  H01L21/76205 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1691

    Abstract: PURPOSE: An RRAM(Resistive Random Access Memory) device with a spacer structure and a fabrication method thereof are provided to improve the reliability of an operation by minimizing the number of filaments which are the conduction route taking part in switching in a resistance variable layer. CONSTITUTION: A resistance variable layer is formed in the form of spacers(42a,42b). The spacers are made of a transition metal oxide with a resistance variable characteristic. The spacers is formed in the sidewall of a first insulating layer which is filled between a bottom electrode(20) and an upper electrode(62). The first insulating layer is formed to be separated at a constant interval between trenches. A second insulating layer(54) is formed on the spacers.

    Abstract translation: 目的：提供一种具有间隔结构及其制造方法的RRAM（电阻随机存取存储器）装置，通过最小化作为电阻变化层切换中的导通路径的长丝的数量来提高操作的可靠性。 构成：电阻变化层形成为间隔物（42a，42b）的形式。 间隔物由具有电阻变化特性的过渡金属氧化物制成。 间隔物形成在填充在底部电极（20）和上部电极（62）之间的第一绝缘层的侧壁中。 第一绝缘层形成为在沟槽之间以恒定的间隔分开。 在间隔件上形成第二绝缘层（54）。

    곤충의 표지 유전자를 이용한, 곤충의 맥주 유입 시기 계산 방법
    8.
    发明公开
    곤충의 표지 유전자를 이용한, 곤충의 맥주 유입 시기 계산 방법 有权
    使用标记基因从食物中分离啤酒的流入时间的计算方法

    公开(公告)号：KR1020120119196A

    公开(公告)日：2012-10-30

    申请号：KR1020110037006

    申请日：2011-04-20

    Applicant: 하이트진로 주식회사 ,  서울대학교산학협력단

    Inventor： 이시혁 ,  강재순 ,  오정훈 ,  임규헌 ,  명기현 ,  최하종

    IPC: C12Q1/68 ,  G06F19/10 ,  G06F17/15

    CPC classification number: C12Q1/6851 ,  G06F19/10

    Abstract: PURPOSE: A calculating method of beer inflow timing of insects by using marker genes of insects is provided to enhance accuracy by drawing quantitative formula. CONSTITUTION: A calculating method of beer inflow timing of insects comprises the following steps: obtaining Ctc which is Ct value of marker gene of control group from the quantitative result of real-time PCR; performing quantitative real-time PCR for marker gene of the standard samples after specific duration is passed from the extinction day of the standard sample; obtaining Ct value of marker gene of the standard sample from the real-time PCR result; obtaining the Cts which is Ct value of the marker gene of the standard sample according to the elapsed time; calculating Ct ratio by using Cts from the second step and Ctc from the first step; and obtaining the standard curve by using the Ct ratio. The control group and the standard sample are allogenic.

    Abstract translation: 目的：通过使用昆虫标记基因，提供昆虫啤酒流入时间的计算方法，通过绘制定量公式提高准确度。 构成：昆虫啤酒流入时间的计算方法包括以下步骤：从实时PCR定量结果中获得对照组标记基因Ct值的Ctc; 从标准样品的灭绝日起经过特定持续时间后，对标准样品的标记基因进行定量实时PCR; 从实时PCR结果获得标准样品的标记基因的Ct值; 根据经过时间获得标准样品的标记基因的Ct值的Cts; 通过使用来自第二步骤的Cts和来自第一步骤的Ctc计算Ct比率; 并通过使用Ct比率获得标准曲线。 对照组和标准样品均为同种异体。

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