Abstract:
본 발명의 실시예에 따른 정렬된 나노선 전사 방법은, 상면에 홈을 갖는 제1 기판의 상기 홈 내에 나노선을 정렬시키는 단계; 및 탄성력과 접착력을 갖는 전사용 부재를 이용하여 상기 제1 기판의 홈 내에 정렬된 나노선을 다른 제2 기판에 옮겨 찍는 단계를 포함한다.
Abstract:
The present invention relates to a device and a method for controlling surface wetting properties of materials and a lab-on-a-chip using the same. The lab-on-a-chip includes a substrate, a channel which is formed on the substrate and forms a movement path for a sample, and a reactive gas supply unit which supplies reactive gas to the channel. The channel is includes a rough surface material which is formed on the substrate and has roughness larger than the substrate and a reactive material which is formed on the rough surface material and changes its volume by reacting with reactive gas.
Abstract:
PURPOSE: A graphene composition, a graphene source, a manufacturing method thereof, and a manufacturing method a graphene film using the same are provided to prevent the graphene aggregation in a graphene solution, and to be able to manufacture the graphene film having high smoothness by a simple process. CONSTITUTION: A graphene composition comprises a polymer material, a first solvent, and a second solvent having a lower surface tension and a higher boiling point than the first solvent. The polymer material is a conductive polymer material. The first solvent is at least any one among deionized water, methanol, dimethylformamide, ethylene glycol, and acetone. A manufacturing method of a graphene source comprises a step of injecting the polymer material in a graphene sheet dispersion solution(S100), and a step of adding a secondary solvent having a lower surface tension and a higher boiling point than the main solvent contained the said solution(S300). The polymer material is at least any one among polypyrrole, polyaniline, polythiophene, and PEDOT:PSSs (poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate)), which are conducting polymer materials. [Reference numerals] (S100) Introducing a conductive polymer material into a graphene solution; (S200) Filtering the conductive polymer material using filtering paper; (S300) Introducing a poor solvent
Abstract:
PURPOSE: A method for aligning nano-wires is provided to effectively align the nano-wires based on hydrophilicity, hydrophobicity, and photo-sensitive patterns. CONSTITUTION: A method for aligning nano-wires includes the following: a photoresist pattern(620) with a hole structure is formed on the upper side of a substrate(610); a nano-wire aqueous solution is supplied to the hole structure; nano-wires(630) is aligned by evaporating the nano-wire aqueous solution; and the photo-sensitive patterns are eliminated. A material for the photo-sensitive is SU-8. The hydrophilicity and the hydrophobicity of the photo-sensitive patterns and the nano-wires are adjusted on the surface of the substrate.
Abstract:
PURPOSE: A multi level cell nonvolatile memory device is provided to overcome interference between devices due to a scale down using a charge trap region to localize and stores a charge. CONSTITUTION: A semiconductor substrate(101) comprises three source/drain regions(105a) per unit cell or more. A charge trapping insulation unit is formed on a semiconductor substrate. The charge trapping insulation unit includes a charge trap region which traps the charge according to the voltage applied to the source/drain region. A gate electrode(150) is formed on the charge trapping insulation unit. The gate electrode has a flat shape of N polygons. The charge trapping region provides a charge trap site which localizes the charge and stores the charge. The source/drain region is arranged on angular points of N polygon formed by the gate electrode.
Abstract:
PURPOSE: A method for transferring aligned nano-wires is provided to effectively transfer aligned nano-wires or nano-wire network to the desired position of a substrate using a transferring unit. CONSTITUTION: Nano-wires(10) are aligned in the groove of a first substrate(101) which includes a groove-shaped three dimensional structure on the upper side. While the nano-wires are aligned on the first substrate, a nano-wire dispersing solution is applied to the three dimensional structure of the first substrate. The nano-wire dispersing solution is dried. The aligned nano-wires are transferred to a second substrate(401) using a transferring unit(301). An eliminating unit separates the nano-wires from the upper side of the first substrate.
Abstract:
PURPOSE: A method for aligning nano-wires using a groove structure, a three dimensional frame for aligning the nano-wires, and a method for manufacturing the three dimensional frame are provided to efficiently align the nano-wires on a desired position in a nano-wire element manufacturing process. CONSTITUTION: A substrate(201) with a three dimensional structure is prepared. Pluralities of trench grooves, in which both inner walls thereof are inclined, are formed in the three dimension structure. A nano-wires(10) dispersed solution is arranged on the three dimensional structure. The solution is dried to align nano-wires in the trench groove along the longitudinal direction of the trench groove. The trench grooves are parallelly expanded. The cross section shapes of the trench grooves are V-shapes or truncated type inverted pyramid shapes.
Abstract:
PURPOSE: A multi-level-cell nonvolatile memory device with a 3D structure and a manufacturing method thereof are provided to sufficiently increase the area of a channel region by forming a recess part with a 3D structure on an active region inside a unit cell. CONSTITUTION: The depression of a reverse pyramid type is formed on an active region of a semiconductor substrate. Three source/drain regions(105a-105d) or more are formed on the semiconductor substrate outside the depression unit per unit cell. A tunneling insulation layer(110) is formed on the inner wall of the depression. A charge trap region is formed on the tunneling insulation layer inside the depression and stores charges. A blocking insulation layer is formed on the charge trap region. A common gate electrode is formed on the blocking insulation layer.