公开(公告)号：KR102018772B1

公开(公告)日：2019-09-05

申请号：KR1020170171057

申请日：2017-12-13

Applicant: 연세대학교 산학협력단

Inventor： 강성호 ,  정민호

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/768

公开(公告)号：KR1020090116942A

公开(公告)日：2009-11-12

申请号：KR1020080042774

申请日：2008-05-08

Applicant: 연세대학교 산학협력단 ,  동국대학교 산학협력단

Inventor： 김재석 ,  송민규 ,  정민호 ,  문준호 ,  이두복

IPC: H03M1/12

CPC classification number: H03M1/368 ,  H03M1/002 ,  H03M1/121 ,  H03M2201/2208 ,  H03M2201/62 ,  H03M2201/93

Abstract: PURPOSE: A folding-interpolating analog to a digital converter using a less track-and-hold circuit is provided to reduce a circuit area and power consumption by connecting a track-and-hold circuit at the end of a folding block stage. CONSTITUTION: In a folding-interpolating analog to a digital converter using a less track-and-hold circuit, a preamplifier stage(210) amplifies an analog signal by using a plurality of reference voltages and produces a plurality of input signals. A folding block stage(230) folds the input signals according to a predetermined folding rate. The folding block stage produces a plurality of folding signals. The track-and-hold stage(250) is arranged at the backend of the folding block stage by receiving the outputs of the folding block stage. The track-and-hold stage track and holds the folding signals.

Abstract translation: 目的：提供使用较少轨道和保持电路的数字转换器的折叠内插模拟，以通过在折叠块级结束时连接跟踪和保持电路来减少电路面积和功耗。 构成：在使用较少轨道和保持电路的数字转换器的折叠内插模拟中，前置放大器级（210）通过使用多个参考电压来放大模拟信号并产生多个输入信号。 折叠台阶（230）根据预定的折叠速率折叠输入信号。 折叠台阶产生多个折叠信号。 跟踪保持阶段（250）通过接收折叠块阶段的输出而被布置在折叠块阶段的后端。 跟踪和保持阶段跟踪并保存折叠信号。