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公开(公告)号：KR101003909B1
公开(公告)日：2010-12-30
申请号：KR1020080075933
申请日：2008-08-04
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/812
Abstract: 본 발명은 포텐셜 웰 베리어 트랜지스터에 관한 것으로, 보다 자세하게는 넓은 밴드 갭과 좁은 밴드 갭이 형성하는 포텐셜 웰을 갖는 장벽층을 이용한 포텐셜 웰 베리어 트랜지스터에 관한 것이다.
본 발명의 이종접합층 구조를 가진 트랜지스터에 있어서, 기판 및 상기 기판 상에 위치하는 버퍼층; 상기 버퍼층 상에 위치하는 제 1장벽층; 상기 제 1장벽층 상에 위치하는 채널층; 상기 채널층 상에 위치하고, 포텐셜 웰을 갖는 제 2장벽층; 및 상기 제 2장벽층 상에 위치하는 캡층을 포함함에 기술적 특징이 있다.
포텐셜 웰, 이종접합구조, 장벽층, 트랜지스터-
公开(公告)号：KR100948575B1
公开(公告)日：2010-03-18
申请号：KR1020080014683
申请日：2008-02-19
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L27/108 , H01L21/306
Abstract: 본 발명은 멀티칩 모듈(MCM-D) 기판에 구현하는 새로운 구조의 금속-절연체-금속(MIM) 캐패시터로서, 실리콘 기판상에 금속-절연체-금속 캐패시터를 위한 마스크 패턴을 형성하는 마스크 패턴 단계, 상기 기판을 습식 식각하는 식각 단계, 상기 마스크 패턴을 제어하는 단계 및 상기 식각된 영역에 금속층, 절연막 그리고 금속층을 차례대로 형성하는 박막 형성 단계에 의해 제조된다.
MIM 캐패시터, 습식 식각, 실리콘 단결정, 역피라미드형 홈-
公开(公告)号：KR1020090104157A
公开(公告)日：2009-10-06
申请号：KR1020080029443
申请日：2008-03-31
Applicant: 재단법인서울대학교산학협력재단
CPC classification number: H03K17/6871 , H03K17/693 , H04B1/44
Abstract: PURPOSE: A high-frequency switching circuit using an enhancement mode transistor is provided to turn on a channel of a power on-state transistor in a VDD which is maximal voltage of a battery in order to operate the transistor in a minimal resistor. CONSTITUTION: A high-frequency switching circuit using an enhancement mode transistor includes a first capacitor(BC1), a capacity through switch element and a capacity shunt switch element. The first capacitor is connected to one end of a high-frequency signal path, and the capacity through switch element is connected between the first capacitor and the other end of the high frequency signal path. One end of the capacity shunt switch element is connected between the first capacitor and the capacity through switch element, and the other end of the capacity shunt switch element is connected between voltage control terminals.
Abstract translation: 目的：提供一种使用增强型晶体管的高频开关电路，以使电源的最大电压为VDD的导通状态晶体管的通道，以将晶体管工作在最小电阻中。 构成：使用增强型晶体管的高频开关电路包括第一电容器（BC1），通过开关元件的容量和容量分流开关元件。 第一电容器连接到高频信号路径的一端，并且通过开关元件的电容连接在第一电容器和高频信号路径的另一端之间。 容量分流开关元件的一端连接在第一电容器和通过开关元件的电容之间，并且容量分流开关元件的另一端连接在电压控制端子之间。
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公开(公告)号：KR1020080093659A
公开(公告)日：2008-10-22
申请号：KR1020070037664
申请日：2007-04-18
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/778
CPC classification number: H01L29/42376 , H01L21/28587 , H01L29/66431 , H01L29/778
Abstract: A high frequency transistor structure by a half self-aligned process using a T-type gate and a method for manufacturing the same are provided to sufficiently increase a distance between a gate and a drain while sufficiently reducing the gate and a source and to reduce parasitic capacitance by reducing an upper portion of the T-type gate and the drain. A method for manufacturing a high frequency transistor structure by a half self-aligned process using a T-type gate includes the steps of: forming a passivation layer(220) on a substrate(200) on which the T-type gate; forming a photo resist between a part of an upper surface of the T-type gate and a formation region of a drain(260); removing the passivation layer using the photo resist; depositing a metal layer on the substrate to form a source(250) and the drain; removing the photo resist and the metal layer on the photo resist; and selectively etching the passivation layer. The photo resist has an over hang structure, and a width of the photo resist ranges from 1 to 1000 um.
Abstract translation: 提供通过使用T型栅极的半自对准工艺的高频晶体管结构及其制造方法来充分增加栅极和漏极之间的距离，同时充分减小栅极和源极并减少寄生 通过减小T型栅极和漏极的上部的电容。 通过使用T型栅极的半自对准工艺制造高频晶体管结构的方法包括以下步骤：在其上形成T型栅极的衬底（200）上形成钝化层（220）; 在T型栅极的上表面的一部分与漏极（260）的形成区域之间形成光刻胶; 使用光刻胶去除钝化层; 在所述衬底上沉积金属层以形成源（250）和所述漏极; 去除光致抗蚀剂和光刻胶上的金属层; 并选择性地蚀刻钝化层。 光致抗蚀剂具有过悬挂结构，光致抗蚀剂的宽度为1〜1000μm。
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公开(公告)号：KR1020080076029A
公开(公告)日：2008-08-20
申请号：KR1020070015421
申请日：2007-02-14
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/778 , B82Y40/00
CPC classification number: H01L21/28587 , H01L29/42376 , H01L29/66462
Abstract: A T-type gate electrode for an HEMT(High Electron Mobility Transistor) and a manufacturing method thereof are provided to improve cut-off frequency characteristics of the HEMT by forming a lower region of the T-type gate electrode in a few tens of nanometers. First to third insulation layers(310,320,330) are formed on an epitaxial structure layer, which is formed by growing plural crystal layers on a semiconductor substrate. A resist pattern(410) is formed on the third insulation layer. A slant surface(440) is formed on the third insulation layer. A predetermined region of the second insulation layer is exposed. The exposed third insulation layer is removed, a slant surface is formed on the second insulation layer, and a portion of the first insulation layer is removed. The exposed region of the first insulation layer is removed. An electrode material is deposited on an etched region.
Abstract translation: 提供了一种用于HEMT（高电子迁移率晶体管）的T型栅电极及其制造方法，用于通过将T型栅电极的下部区域形成几十纳米来提高HEMT的截止频率特性 。 第一至第三绝缘层（310,320,330）形成在通过在半导体衬底上生长多个晶体层而形成的外延结构层上。 在第三绝缘层上形成抗蚀剂图案（410）。 在第三绝缘层上形成倾斜表面（440）。 露出第二绝缘层的预定区域。 去除暴露的第三绝缘层，在第二绝缘层上形成倾斜表面，并且去除第一绝缘层的一部分。 去除第一绝缘层的暴露区域。 电极材料沉积在蚀刻区域上。
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Patent Agency Ranking
公开(公告)号：KR1020080071653A
公开(公告)日：2008-08-05
申请号：KR1020070009755
申请日：2007-01-31
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/302 , H01L21/336
CPC classification number: H01L29/66477 , H01L21/0272
Abstract: A method of forming a multiple gate using a metal lift-off process is provided to reduce a manufacturing time and a manufacturing cost of a semiconductor device by decreasing an inter-gate distance in the multiple gate. A polymer layer is formed on a substrate(300) and the polymer layer is patterned. An isotropy etching process is performed on an exposed substrate. Metal layers(340,350) are formed on the substrate. The polymer layer and the metal layer, which is formed on the polymer layer, are removed. A thickness of the polymer layer lies between 100 and 500 nm. The polymer is a photoresist. The polymer layer is patterned by using a photolithography process or an electron beam lithography process.
Abstract translation: 提供了使用金属剥离工艺形成多栅极的方法，以通过减小多栅极中的栅极间距来减少半导体器件的制造时间和制造成本。 在基板（300）上形成聚合物层，并且对聚合物层进行图案化。 在曝光的基板上执行各向同性蚀刻工艺。 金属层（340,350）形成在基板上。 除去形成在聚合物层上的聚合物层和金属层。 聚合物层的厚度在100和500nm之间。 聚合物是光致抗蚀剂。 通过使用光刻工艺或电子束光刻工艺对聚合物层进行图案化。
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公开(公告)号：KR100969494B1
公开(公告)日：2010-07-13
申请号：KR1020080015082
申请日：2008-02-20
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/336
Abstract: 본 발명은 2층의 레지스트를 사용하여 T-게이트와 게이트 리세스를 형성하는 방법에 대한 것이다. 특히, 본 발명에 따른 T-게이트 및 게이트 리세스 형성방법은 간단히 비대칭 T-게이트(감마 게이트)를 형성하는 동시에 비대칭 게이트 리세스를 형성할 수 있다. 2층의 레지스트는 기판상의 제1레지스트와 그 제1레지스트상의 제2레지스트로 형성되며, 특히 제2레지스트로서 화학 증폭형 레지스트(chemically amplified resist)를 사용함으로써 본 발명의 목적을 달성할 수 있다.
화학 증폭형 레지스트, T-게이트, 고전자이동도 트렌지스터, 비대칭형 게이트 리세스-
公开(公告)号：KR100967847B1
公开(公告)日：2010-07-05
申请号：KR1020080029443
申请日：2008-03-31
Applicant: 재단법인서울대학교산학협력재단
Abstract: 본 발명에 의한 고주파 스위치 회로는 DC 블럭킹 커패시터(DC blocking capacitor)를 이용하여 각 트랜지스터를 DC 적으로 분리하여 오프 상태 트랜지스터를 더 deep pinch off시키고, 온 상태 트랜지스터에 최대 전류가 흐르는 바이어스를 제공한다. 또한 증식형(Enhancement mode) 트랜지스터를 사용하여 공핍형(depletion mode) 트랜지스터에 비해 같은 게이트 전압으로 더 deep pinch off시킬 수 있고 고주파 스위치가 큰 Pmax를 갖도록 한다.
고주파 스위치 회로, DC 블럭킹 커패시터, 증식형 트랜지스터-
公开(公告)号：KR1020090089923A
公开(公告)日：2009-08-25
申请号：KR1020080015082
申请日：2008-02-20
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/336
CPC classification number: H01L29/66621 , H01L21/28114 , H01L29/4236
Abstract: A gate recess and a method for forming a gate are provided to reduce a process cost by not requiring an additional electronic beam lithography process. A first resist layer(110) is formed on a substrate(100). A pattern of a gate foot is formed in the first resist layer. A second resist layer(150) is formed on the first resist layer. The pattern of the gate head is formed in the second resist layer. The substrate is etched. The pattern of the gate foot inclines to a source(130) and forms a gamma gate pattern.
Abstract translation: 提供了一种栅极凹槽和用于形成栅极的方法，以通过不需要额外的电子束光刻工艺来降低工艺成本。 在基板（100）上形成第一抗蚀剂层（110）。 在第一抗蚀剂层中形成栅极脚的图形。 在第一抗蚀剂层上形成第二抗蚀剂层（150）。 门头的图案形成在第二抗蚀剂层中。 衬底被蚀刻。 栅极脚的图案倾斜到源极（130）并形成伽马栅极图案。
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公开(公告)号：KR100873933B1
公开(公告)日：2008-12-15
申请号：KR1020070037664
申请日：2007-04-18
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/778
Abstract: A high frequency transistor structure by a half self-aligned process using a T-type gate and a method for manufacturing the same are provided to sufficiently increase a distance between a gate and a drain while sufficiently reducing the gate and a source and to reduce parasitic capacitance by reducing an upper portion of the T-type gate and the drain. A method for manufacturing a high frequency transistor structure by a half self-aligned process using a T-type gate includes the steps of: forming a passivation layer(220) on a substrate(200) on which the T-type gate; forming a photo resist between a part of an upper surface of the T-type gate and a formation region of a drain(260); removing the passivation layer using the photo resist; depositing a metal layer on the substrate to form a source(250) and the drain; removing the photo resist and the metal layer on the photo resist; and selectively etching the passivation layer. The photo resist has an over hang structure, and a width of the photo resist ranges from 1 to 1000 um.
Abstract translation: 通过使用T型栅极的半自对准工艺的高频晶体管结构及其制造方法被提供以充分地增加栅极和漏极之间的距离，同时充分地减小栅极和源极并且减少寄生 通过减小T型栅极和漏极的上部来实现电容。 一种通过使用T型栅极的半自对准工艺来制造高频晶体管结构的方法包括以下步骤：在衬底（200）上形成钝化层（220），其上形成有T型栅极; 在所述T型栅极的上表面的一部分与漏极（260）的形成区域之间形成光刻胶; 使用光刻胶去除钝化层; 在衬底上沉积金属层以形成源极（250）和漏极; 去除光刻胶上的光刻胶和金属层; 并选择性地蚀刻钝化层。 光阻具有悬挂结构，并且光阻的宽度范围从1到1000μm。
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