Abstract:
스토리지 디바이스는 채널별로 그룹화된 복수의 불휘발성 메모리들을 구비하는 저장 매체 및 상기 불휘발성 메모리들을 채널별로 제어하는 SSD 컨트롤러를 포함한다. 상기 SSD 컨트롤러는 하나의 채널에 대한 프로그램 데이터를 병렬로 인코딩하여 상기 하나의 채널에 연결되는 불휘발성 메모리들에 제공하고, 하나의 채널로부터의 독출 데이터를 재인코딩하여 상기 독출 데이터에 대한 패리티 데이터를 생성하고, 상기 패리티 데이터를 이용하여 상기 독출 데이터에 대한 디코딩을 병렬로 수행한다.
Abstract:
PURPOSE: A multi-thread BCH encoder, a BCH decoder, a storage device including the same, and a storage system are provided to correct SSD errors of multiple channels using one encoder and one decoder. CONSTITUTION: A syndrome computation block (410) generates syndrome values by computing a plurality of bits of parity data generated from read data in parallel. A folded Berleykamp-Massey (BM) block (420) generates an error position polynomial based on the syndrome values. A chien search block (430) calculates an error position in parallel based on the error position polynomial. An error corrector corrects errors of the read data based on the error position and outputs the corrected data.
Abstract:
연접 비씨에이치 인코딩 회로는 로우 인코더, 칼럼 인코더 및 패리티 선입 선출 버퍼를 포함한다. 상기 로우 인코더는 하나의 페이지를 구성하는 복수의 데이터 블록들에 대하여 로우 방향으로 제1 인코딩을 수행하여 제1 패리티들을 병렬로 생성한다. 상기 칼럼 인코더는 상기 데이터 블록들에 대한 상기 제1 인코딩이 수행되는 동안 상기 데이터 블록들 각각에 대한 제2 인코딩을 수행하여 칼럼 방향의 부분 패리티들을 생성한다. 상기 패리티 선입선출 버퍼는 상기 부분 패리티들을 저장한다. 상기 칼럼 인코더는 상기 패리티 선입선출 버퍼에 저장된 부분 패리티들을 이용하여 상기 복수의 데이터 블록들에 대한 한번의 독출로 상기 복수의 데이터 블록들에 대하여 칼럼 방향으로 상기 제2 인코딩을 수행하여 제2 패리티들을 생성한다.
Abstract:
A BCH decoder contains a syndrome calculation block, a key-equation solver, a Ziehen search block, and an error correction block. The syndrome calculation block generates syndrome values from a received code word. The key-equation solver generates an error location polynomial based on the syndrome values. The Ziehen search block calculates the position of the error on the basis of the error location polynomial. The error correction block outputs the corrected code word by correcting the error of the received code word on the basis of the position of the error. The key-equation solver generates immediately the error position polynomial without running the calculation if one error exists in the received code word.
Abstract:
PURPOSE: A BCH decoder, a memory system including the same and a decoding method are provided to reduce complexity of hardware without increasing a critical delay of hardware. CONSTITUTION: A decoder(10) includes a syndrome calculation block(100), a key equation solver(210), a Chien search block(220) and an error correction block(230). The syndrome calculation block generates syndrome values from a received code word. The key equation solver generates an error position polynomial based on the syndrome values. The Chien search block calculates an error position based on the error position polynomial. The error correction block corrects an error of the received code word based on the error position and outputs the corrected code word.
Abstract:
A concatenated BCH encoding circuit includes a row encoder, a column encoder, and a parity FIFO buffer. The lower encoder performs first encoding in a row direction with respect to a plurality of data blocks forming one page and generates firs parities in parallel. The column encoder performs second encoding for each data block during the first encoding for the data blocks and generates partial parities in a column direction. The parity FIFO buffer stores the partial parities. The column encoder performs the second encoding in the column direction with respect to the data blocks by one read-out for the data blocks using the partial parities stored in the parity FIFO buffer and generates second parities.
Abstract:
PURPOSE: A BHC decoder, a memory system including the same, and a BHC decoding method are provided to reduce hardware complexity by applying BM algorithm in a KES block of a BCH decoder. CONSTITUTION: A syndrome computation block generates syndrome values from a received code word. A key-equation solver generates an error location polynomial based on the syndrome values. A key-equation solver(200) comprises a plurality of registers, a plurality of multiplexers(212), a plurality of adders(213), and a plurality of GF multiplexers(214). A Chien search block calculates an error location based on an error location polynomial. An error correction block outputs the corrected codeword by correcting the error of the code word.
Abstract:
PURPOSE: A reed-solomon decoder, a memory system thereof and a decoding method thereof are provided to reduce complexity of hardware by sharing substructures unnecessarily overlapping from a reed-solomon decoder. CONSTITUTION: A syndrome computation block(100) generates the values of syndrome from received code word. A key-Equation Solver(210) generates a polynomial expression of error value and a polynomial expression of error location based on values of the syndrome. A chien search and pony block(220) calculate error locations and error values based on error locator polynomial expression and error value polynomial expression. An error correction block(230) outputs corrected cord word based on the error location and the error value. The syndrome value block generates the syndrome values using one matrix product.