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公开(公告)号:KR1019920010970B1
公开(公告)日:1992-12-26
申请号:KR1019900021863
申请日:1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit generates the control signal that represents the state of the data block stored in a cache memory with high speed to improve the efficiency of bus usage. It includes an electrically programmable memory (EPM) for receiving write-backing signal (WBING), parity error signal of bus (BPERR), acting signal (ACT), time pulse (TP), bus address deciding signal (BA-SELF), tag-match signal (TG-MATCH) etc. froma controller, outputting one of the control signals (SHARED,SNACK,DIRTY) through one of I/O12, I/O13 and I/O14, and driving bus control signals (BUS-SHARED, BUS- SNACK, BUS-DIRTY) to be zero through NAND gates (N1,N2,N3).
Abstract translation: 电路以高速生成表示存储在高速缓冲存储器中的数据块的状态的控制信号,以提高总线使用的效率。 它包括用于接收写背信号(WBING),总线奇偶校验错误信号(BPERR),作用信号(ACT),时间脉冲(TP),总线地址决定信号(BA-SELF)等)的电可编程存储器(EPM) 标签匹配信号(TG-MATCH)等,通过I / O12,I / O13和I / O14之一输出控制信号(SHARED,SNACK,DIRTY)之一,以及驱动总线控制信号(BUS- 共享,BUS-SNACK,BUS-DIRTY)通过NAND门(N1,N2,N3)为零。
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