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公开(公告)号：KR1019920009442B1
公开(公告)日：1992-10-16
申请号：KR1019900021864
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/12
Abstract: The snoop controller generates control signal necessary for cache coherence protocol according to address signals related to memory cycle within one period of timer pulse. The controller includes a write address comparators (2-5) for comparing bus address signal with write back address signal detected at every rising edge of control signal to generate write address match signal, read address comparators (10-13) for comparing bus address signal with read address signal detected at every vising edge of timing pulses to generate read address match signal, a first program enable memory (15) for generating bus parity error signal and acting signal according to bus address space signal, bus address enable signal, and snoop action stop signal, a second program enable memory (16) for generating write back going signal and a third program enable memory (17) for generating state memory write enable signal and data input signal.
Abstract translation: 侦听控制器根据与定时器脉冲的一个周期内的存储器周期相关的地址信号，产生高速缓存一致性协议所需的控制信号。 控制器包括用于比较总线地址信号和在控制信号的每个上升沿检测到的回写地址信号以产生写入地址匹配信号的写入地址比较器（2-5），用于比较总线地址信号的读取地址比较器（10-13） 具有在定时脉冲的每个边缘处检测到读取地址信号以产生读取地址匹配信号;第一编程使能存储器（15），用于根据总线地址空间信号，总线地址使能信号和窥探产生总线奇偶校验错误信号和作用信号 动作停止信号，用于产生回写信号的第二程序使能存储器（16）和用于产生状态存储器写使能信号和数据输入信号的第三程序使能存储器（17）。
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公开(公告)号：KR1019920010970B1
公开(公告)日：1992-12-26
申请号：KR1019900021863
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit generates the control signal that represents the state of the data block stored in a cache memory with high speed to improve the efficiency of bus usage. It includes an electrically programmable memory (EPM) for receiving write-backing signal (WBING), parity error signal of bus (BPERR), acting signal (ACT), time pulse (TP), bus address deciding signal (BA-SELF), tag-match signal (TG-MATCH) etc. froma controller, outputting one of the control signals (SHARED,SNACK,DIRTY) through one of I/O12, I/O13 and I/O14, and driving bus control signals (BUS-SHARED, BUS- SNACK, BUS-DIRTY) to be zero through NAND gates (N1,N2,N3).
Abstract translation: 电路以高速生成表示存储在高速缓冲存储器中的数据块的状态的控制信号，以提高总线使用的效率。 它包括用于接收写背信号（WBING），总线奇偶校验错误信号（BPERR），作用信号（ACT），时间脉冲（TP），总线地址决定信号（BA-SELF）等）的电可编程存储器（EPM） 标签匹配信号（TG-MATCH）等，通过I / O12，I / O13和I / O14之一输出控制信号（SHARED，SNACK，DIRTY）之一，以及驱动总线控制信号（BUS- 共享，BUS-SNACK，BUS-DIRTY）通过NAND门（N1，N2，N3）为零。
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Patent Agency Ranking
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公开(公告)号：KR1019930007050B1
公开(公告)日：1993-07-26
申请号：KR1019900021862
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The snoop controller provides a pended bus protocol which enables data to be read always correctly in multiple processors. It includes comparators (4,5) for comparing the address from a bus with the contents of an internal tag comparator (7) and a status memory (8), and a decoder (2) for applying SNACK signal to the bus to provide the time for cache coherence when the result of the comparator (5) is true.
Abstract translation: 监听控制器提供了一种挂起总线协议，使得数据可以在多个处理器中始终正确读取。 它包括用于将来自总线的地址与内部标签比较器（7）和状态存储器（8）的内容进行比较的比较器（4,5），以及用于将SNACK信号施加到总线以提供 当比较器（5）的结果为真时，缓存一致性的时间。
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