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公开(公告)号：KR100268178B1
公开(公告)日：2000-10-16
申请号：KR1019970072050
申请日：1997-12-22
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: PURPOSE: A PCI apparatus having a cache function is provided to minimize a standby time of a response with respect to an access of a PCI bus for thereby enhancing a performance of an entire system by providing a caching function so that a PCI is not occupied for long time in a system which uses a slow access time. CONSTITUTION: A PCI interface controller(PCIIFC)(10) includes a configuration register(11), an address decoder(12), a transfer type comparator(13), and a PCI stage machine(14). An address comparator(ADEC)(12) analyzes an address driven in an address phase of a PCI bus cycle and checks whether a memory connected with the CTU is accessed. A local cache control module(LCCM)(20) includes local cache memories(22, 23) in the CTU, an LCC(21) for controlling the cache memory, a PCI address buffer(ADDBUF)(25) for storing an address from the PCI address buffer, and a data buffer(260 for storing the PCI write data. A TAG memory(23) stores an address by the direct cache address mapping method for checking whether the cache data memory(22) has the data with respect to the read cycle performed in the PCI. The LCC(21) generates a signal for controlling the ADDBUF(25) and signals(206, 207) for controlling the WDBUF(26). The ADDBUF(25) is a buffer capable of storing the address of the cycle which is performed through the PCI bus.
Abstract translation: 目的：提供一种具有高速缓存功能的PCI设备，以最小化相对于PCI总线访问的响应的待机时间，从而通过提供缓存功能来提高整个系统的性能，使得PCI不被占用 长时间在使用缓慢访问时间的系统中。 构成：PCI接口控制器（PCIIFC）（10）包括配置寄存器（11），地址解码器（12），传输类型比较器（13）和PCI级机器（14）。 地址比较器（ADEC）（12）分析在PCI总线周期的地址相位中驱动的地址，并检查与CTU连接的存储器是否被访问。 本地高速缓存控制模块（LCCM）（20）包括CTU中的本地高速缓冲存储器（22,23），用于控制高速缓冲存储器的LCC（21），用于存储来自 PCI地址缓冲器和数据缓冲器（260，用于存储PCI写入数据），TAG存储器（23）通过直接高速缓存地址映射方法存储地址，用于检查高速缓存数据存储器（22）是否具有相对于 在PCI中执行读周期，LCC（21）产生用于控制ADDBUF（25）的信号和用于控制WDBUF（26）的信号（206,207），ADDBUF（25）是一种能够存储 通过PCI总线执行的周期地址。
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公开(公告)号：KR1019990052557A
公开(公告)日：1999-07-15
申请号：KR1019970072050
申请日：1997-12-22
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: 본 발명은 캐쉬 기능을 가지는 피시아이(Peripheral Component Interconnect;이하, PCI라함) 장치에 관한 것으로, 특히 PCI 버스를 사용하는 컴퓨터 시스템에서, PCI 버스에 연결된 장치에 캐쉬 기능을 가지도록 하여PCI 버스를 통하여 여러가지 자원에 접근하는 사이클에 대해 빠른 접근이 이루어질 수 있도록 한 PCI장치에 관한 것이다.
PCI 버스는 자체에 빠른 주파수와 폭 넓은 어드레스/데이터 버스를 가지고 있기 때문에 최근 들어 널리 사용되고 있다. 그러나 외부 장치에 연결되는 여러 메모리, 디스크, 그리고 네트워크 자원 등은 각 자원들의 특성에 따른 지연 시간으로 인해 PCI 버스의 빠른 속도를 따라가지 못한다.
따라서 본발명은 늦은 지연 시간을 가지는 지역 메모리를 접근하는 사이클에 대해서 쓰기가 수행되면 캐쉬 메모리에 이 데이터 값을 써넣고는 바로 쓰기 사이클을 완료한다. 그리고 이 데이터를 PCI 버스 접근과 상관없이 늦은 메모리에 써넣는다. 캐쉬 메모리에 저장된 데이터를 PCI 버스를 통해서 요구하게 되면, 즉시 캐쉬 메모리에서 데이터를 보낼 수가 있다 이렇게 읽기와 쓰기를 캐쉬 메모리를 통하여 수행하게 하여 전체적으로 시스템의 성능을 향상시킨다.-
3.发明授权다중프로세서 인터럽트 요청기에서의 인터럽트 송신 및 완료 제어방법(Control scheme of interrupt go and done in a multiprocessor interrupt requester) 失效一种在多处理器中断请求器中控制中断传输和完成的方法，所述方法包括：
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公开(公告)号：KR1019960002029A
公开(公告)日：1996-01-26
申请号：KR1019940012745
申请日：1994-06-07
Applicant: 한국전자통신연구원
IPC: G06F13/24
Abstract: 본 발명은 다중프로세서 인터럽트 요청기에서의 전송실패 인터럽트의 구동방법에 관한 것으로서, 본 발명에서는 프로세서간 인터럽트의 전송실패 인터럽트신호 (TFINT)가 구동되지 않았고 응답정보를 검사하는 CHECK 상태이고 전송오류가 발생하였고 유한 재시도 조건에서 재시도 회수가 만료되었고 전송실패 인터럽트 구동이 허용되었을 경우를 인지하여 전송실패 인터럽트 신호(TFINT)를 1로 구동하고, 구동한 전송실패 인터럽트 신호를 철회하는 조건인 전송실패 인터럽트가 이미 구동되어 있고 TMR읽기나 CSR읽기가 발생하는 경우를 인지하여 구동한 전송실패 인터럽트를 철회하는 방법을 제공한다.
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Patent Agency Ranking
公开(公告)号：KR1019960001092B1
公开(公告)日：1996-01-18
申请号：KR1019930024330
申请日：1993-11-16
Applicant: 한국전자통신연구원
IPC: G06F1/06
Abstract: initializing a timer; repeating the above operation until a raising edge by checking the raising edge; checking a value of a CCR when a clock is at the raising edge; in case of a value "0", copying a MCR on the CCR; in case that the CCR is not 0" and a BCR is not "0", checking whether the BCR is "0" or not; in case that the CCR is "1" and the BCR is "0", copying the MCR on the CCR, and the MCR on the BCR; checking whether the CCR is not "1" and whether the BCR is "0"; in case that the BCR is "0", reducing the CCR by 1, copying it on the BCR; and in case that the BCR is not "0", reducing the value of the BCR by 1.
Abstract translation: 初始化一个定时器; 通过检查提升边缘重复上述操作直到升起边缘; 当时钟处于上升沿时检查CCR的值; 在值“0”的情况下，复制CCR上的MCR; 在CCR不为0“且BCR不为”0“的情况下，检查BCR是否为”0“;如果CCR为”1“且BCR为”0“，则复制MCR CCR和BCR上的MCR;检查CCR是否不是“1”，以及BCR是否为“0”;如果BCR为“0”，则将CCR减少1，将其复制到BCR上; 并且在BCR不为“0”的情况下，将BCR的值减小1。
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公开(公告)号：KR1019950010831B1
公开(公告)日：1995-09-23
申请号：KR1019930024329
申请日：1993-11-16
Applicant: 한국전자통신연구원
IPC: G06F9/46
Abstract: initiating a timer to be programmed, driving a time-out interrupt signal to be "0", and becoming a value of tag bit "0"; executing a clock counting until an input clock to the timer is a rising edge; if the rising edge, generating a time-out in which a value of a current count register as "1" and a value of a base count register as "0"; driving the time-out interrupt signal whenever the time-out is generated and determining whether the clock is the rising edge; if the value of the current count register is not "1" and the value of base count register is not "0", if the time-out interrupt signal is not driven, returning to the executing the clock counting step; if the time-out interrupt signal is driven and the tag bit value is "3", withdrawing the drive of the time-out interrupt signal to change the tag bit value into "0"; if the time-out interrupt signal is driven and the tag bit value is not "3", increasing the tag bit value by "1" and returning to the executing the clock counting step.
Abstract translation: 启动要编程的定时器，将超时中断信号驱动为“0”，并变为标签位“0”的值; 执行时钟计数，直到定时器的输入时钟为上升沿; 如果上升沿，则产生其中当前计数寄存器的值为“1”的超时值和基本计数寄存器的值为“0”; 每当产生超时时驱动超时中断信号，并确定时钟是否是上升沿; 如果当前计数寄存器的值不为“1”，并且基本计数寄存器的值不为“0”，则如果超时中断信号未被驱动，则返回执行时钟计数步骤; 如果超时中断信号被驱动并且标签位值为“3”，则取出超时中断信号的驱动，将标记位值改变为“0”; 如果驱动超时中断信号并且标签位值不为“3”，则将标签位值增加“1”并返回到执行时钟计数步骤。
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公开(公告)号：KR1019950010828B1
公开(公告)日：1995-09-23
申请号：KR1019930024327
申请日：1993-11-16
Applicant: 한국전자통신연구원
IPC: G06F9/00
Abstract: resetting a timer to be programmed; determining whether a clock inputted to the timer is a rising edge; if the rising edge, determining whether an address strobe signal for reading or writing first and second registers within the timer is "1"; if the signal is "1", decoding a given address signal by a process interface circuit; if the given address signal indicates the first register within the timer, determining whether a write and read request signal provided to the first register by the process interface circuit is "1"; if the signal is "1", after performing a write operation in byte unit in the first register by a byte enable signal corresponding to each of bytes of the first register, driving a write request completion signal to return to the step determining whether the clock is the rising edge; if the given address signal indicates the second register within the timer, determining whether the write and read request signal provided to the second register by the process interface circuit is "1"; if the signal is not "1", after performing a read operation in byte unit in the second register by a byte enable signal corresponding to each of bytes of the second register, driving a read request completion signal to return to the step determining whether the clock is the rising edge; and if not, driving only the write request completion signal to return to reset the timer.
Abstract translation: 复位要编程的定时器; 确定输入到定时器的时钟是否是上升沿; 如果上升沿，确定用于读或写定时器内的第一和第二寄存器的地址选通信号是否为“1”; 如果信号为“1”，则通过处理接口电路对给定地址信号进行解码; 如果给定地址信号指示定时器内的第一寄存器，则确定由处理接口电路提供给第一寄存器的写和读请求信号是否为“1”; 如果信号为“1”，则在通过与第一寄存器的每个字节相对应的字节使能信号在第一寄存器中以字节为单位执行写操作之后，驱动写请求完成信号返回到确定时钟 是上升的缘故 如果给定的地址信号指示定时器内的第二寄存器，则确定由处理接口电路提供给第二寄存器的写和读请求信号是否为“1”; 如果信号不是“1”，则在通过与第二寄存器的每个字节对应的字节使能信号在第二寄存器中以字节为单位执行读取操作之后，驱动读取请求完成信号以返回到步骤 时钟是上升的缘故; 如果不是，仅驱动写入请求完成信号返回以重置定时器。
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公开(公告)号：KR1019940005778B1
公开(公告)日：1994-06-23
申请号：KR1019910025587
申请日：1991-12-31
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The access arbitrating circuit includes a program device for generating combination signals, an AND gate, a first register synchronized with the output signal of the AND gate, a second register synchronized with a clock pulse, a comparator for comparing the output signals of the first and second registers, a first flip-flop synchronized with a delayed clock pulse, a second flip-flop for generating a signal enabling the comparator, an OR gate, and a third flip-flop synchronized with the delayed clock pulse, thereby improving the performance of a system.
Abstract translation: 访问仲裁电路包括用于产生组合信号的编程装置，与门，与AND门的输出信号同步的第一寄存器，与时钟脉冲同步的第二寄存器，比较器，用于比较第一和 第二寄存器，与延迟时钟脉冲同步的第一触发器，用于产生使能比较器的信号的第二触发器，或与延迟时钟脉冲同步的OR门和第三触发器，由此提高 一个系统。
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