-
-
-
-
公开(公告)号：KR1020000026748A
公开(公告)日：2000-05-15
申请号：KR1019980044409
申请日：1998-10-22
Applicant: 한국전자통신연구원
IPC: H01L21/768
Abstract: PURPOSE: A method for a channel wiring using a horizontal latent reiterated table and a net high and low relationship table is provided to reduce a time for calculation and the number of via by detecting a wiring reiteration and encoding a candidate solution. CONSTITUTION: A method for a channel wiring using a horizontal latent reiterated table and a net high and low relationship table comprises the steps of: encoding candidate solutions representing a solution for a channel wiring; composing a horizontal latent reiterated table and a bet high and low relation ship table from an input net data; composing the candidate solutions; detecting a horizontal reiteration and a vertical reiteration of different nets of the candidate solutions; and generating the candidate solutions and obtaining the solution until the candidate solution not having the reiteration is found.
Abstract translation: 目的：提供一种使用水平潜在重复表和净高低关系表的通道布线的方法，以通过检测布线重复和候选解码的编码来减少计算时间和通孔数。 构成：使用水平潜在重复表和净高低关系表的通道布线的方法包括以下步骤：编码表示用于通道布线的解的候选解; 从输入网络数据构成水平潜在重复表和下注高低关系船表; 撰写候选解决方案; 检测候选解决方案的不同网络的横向重复和垂直重复; 并产生候选解决方案并获得解决方案，直到找到不具有重复的候选解决方案。
-
公开(公告)号：KR1019960015587B1
公开(公告)日：1996-11-18
申请号：KR1019940007851
申请日：1994-04-14
Applicant: 한국전자통신연구원
IPC: G06F13/28
Abstract: a DMAC state controller(8) for controlling the operation about the data transmission with a system bus; a DMAC control/state register(9) for storing control signal and state of the state controller(8); a system bus address generator(10) for generating an address for the data transmission to the system bus; and a buffer RAM address/control generator(11) for generating a buffer RAM address and its control signal by receiving an address from a processor to transmit data to a buffer RAM(15).
Abstract translation: 用于通过系统总线控制关于数据传输的操作的DMAC状态控制器（8）; 用于存储控制信号的DMAC控制/状态寄存器（9）和状态控制器（8）的状态; 系统总线地址发生器（10），用于产生用于数据传输到系统总线的地址; 以及缓冲RAM地址/控制生成器（11），用于通过从处理器接收地址以将数据发送到缓冲RAM（15）来产生缓冲RAM地址及其控制信号。
-
Patent Agency Ranking
公开(公告)号：KR1019950014186B1
公开(公告)日：1995-11-22
申请号：KR1019930027857
申请日：1993-12-15
Applicant: 한국전자통신연구원
IPC: G06F13/28
Abstract: The controller comprises; a system memory address count register(14) which stores and counts addresses to access to the system bus; a data buffer memory address count register(15) which stores and counts the address to access to the data buffer memory; a word count register(13) which stores and counts words in order to control the data for transmitting to the memory; a control register(11) which controlls the operation of the DMA controller; a state register(10) which stores the error state that generates when DMA controller transmits the data; a word register(7) which is the temporary register to retry without interference when the error happens; and a control logic(12) which combines the data buffer memory address register, the system memory addres register and the processor.
Abstract translation: 控制器包括 系统存储器地址计数寄存器（14），其存储和计数访问系统总线的地址; 数据缓冲存储器地址计数寄存器（15），用于存储和计数访问数据缓冲存储器的地址; 字计数寄存器（13），其存储和计数字以便控制用于发送到存储器的数据; 控制DMA控制器的操作的控制寄存器（11）; 状态寄存器（10），存储当DMA控制器发送数据时产生的错误状态; 一个字寄存器（7），它是临时寄存器，在发生错误时不受干扰地重试; 以及组合数据缓冲存储器地址寄存器，系统存储器寄存器和处理器的控制逻辑（12）。
-
公开(公告)号：KR1019950020095A
公开(公告)日：1995-07-24
申请号：KR1019930027857
申请日：1993-12-15
Applicant: 한국전자통신연구원
IPC: G06F13/28
Abstract: 본 발명은 DMA 컨트롤러에 관한 것으로, 어드레스 통로를 분리하여 DMA 컨트롤러가 양쪽 메모리에 동시에 접근하게 하므로써 데이타의 전송능력을 개선시킨 DMA 컨트롤러에 관한 것이다.
상기 DMA 컨트롤러는 시스템 메모리 어드레스를 카운트하는 레지스터(14)와 데이타 버퍼 메모리 어드레스 카운트 레지스터(15)가 각각 공통의 버스에 연결되어 있다. 그리고 DMA 컨트를러의 동작을 제어하는 제어 레지스터(11)와, 에러 상태등을 저장하는 상태 레지스터(10)와, 데이타 전송도중 오류발생시 DMA 컨트롤러가 독립적으로 재시도를 행하기 위하여 초기값을 저장하는 임시 레지스터들(7, 8, 9)이 스텍구조를 이루고 워드를 카운트 하는 레지스터(13)가 공통의 버스에 연결되어 있고, 프로세서(I)와 정합되어 있고 데이타 버퍼(5)를 제어하고 내부상태 천이 제어및 필요한 신호를 생성하는 제어로직이 있다.
상기한 구성에 의한 본 발명은 DMA 컨트롤러가 양쪽 메모리에 동시에 접근하여 많은 양의 정보의 데이타를 짧은 시간에 전송하고, 에러발생시 독자적으로 재시도를 할 수 있고, 데이타 버퍼를 DMA 컨트롤러와 분리하여 데이타 전송 쪽을 가변적이 되도록 하였다.-
公开(公告)号：KR100077205B1
公开(公告)日：1994-09-07
申请号：KR1019900017339
申请日：1990-10-29
Applicant: 한국전자통신연구원
IPC: H04L12/933 , H04L12/947
-
-
公开(公告)号：KR1019930005844B1
公开(公告)日：1993-06-25
申请号：KR1019900017338
申请日：1990-10-29
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The device for transmitting the control signal and the data simultaneously through the set pass comprises: a tag interpretation circuit (1) outputting the signal for a pass setting; an overlap demanding inhibit circuit (2) sending the line connecting signal and the blocking signal; a pass status storing circuit (3) storing the present set pass status by inputting the reset signal and the clock signal; an auxiliary control signal circuit (4) transfering the answer signal, the blocking signal and the control signal to the input/output port; a pass control circuit (5) controlling the connecting status of the input/output port by outputting the control signal.
Abstract translation: 用于通过设定通过同时发送控制信号和数据的装置包括：标签解释电路（1），输出用于通过设置的信号; 重叠要求禁止电路（2）发送线路连接信号和阻塞信号; 通过状态存储电路（3），通过输入复位信号和时钟信号来存储当前的设定通过状态; 辅助控制信号电路（4）将应答信号，阻塞信号和控制信号传送到输入/输出端口; 通过控制电路（5），通过输出控制信号来控制输入/输出端口的连接状态。
-
-
-
-
-
-
-
-
-
Search Results
47
records
(took 0.035 seconds)
