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    도핑 베리어를 가지는 자기 정렬 박막 트랜지스터 및 그 제조 방법
    3.
    发明公开
    도핑 베리어를 가지는 자기 정렬 박막 트랜지스터 및 그 제조 방법 审中-实审
    自对准薄膜晶体管及其制造方法

    公开(公告)号：KR1020140021096A

    公开(公告)日：2014-02-20

    申请号：KR1020120086234

    申请日：2012-08-07

    Applicant: 한국전자통신연구원

    Inventor： 황치선 ,  박상희 ,  오힘찬

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/45

    Abstract: The present invention relates to a self-aligned thin film transistor with a doping barrier for controlling the diffusion level of a doping barrier using the doping barrier in a thin film transistor having a self-alignment structure and a manufacturing method thereof. A self-aligned thin film transistor with a doping barrier includes an active layer formed on a substrate and having a first doping region, a second doping region and a channel region, a gate insulating layer formed on the channel region, a gate electrode formed on the gate insulating layer, a doping source layer formed on the first and the second doping region, a doping barrier formed between the doping source and the first and the second doping region.

    Abstract translation: 本发明涉及具有掺杂势垒的自对准薄膜晶体管，该掺杂势垒用于在具有自对准结构的薄膜晶体管及其制造方法中使用掺杂势垒来控制掺杂势垒的扩散级。 具有掺杂势垒的自对准薄膜晶体管包括形成在衬底上并具有第一掺杂区，第二掺杂区和沟道区的有源层，形成在沟道区上的栅极绝缘层，形成在栅极上的栅电极 栅极绝缘层，形成在第一和第二掺杂区域上的掺杂源层，形成在掺杂源与第一和第二掺杂区之间的掺杂势垒。

    산화물 박막 트랜지스터의 제조 방법
    4.
    发明公开
    산화물 박막 트랜지스터의 제조 방법 审中-实审
    制造氧化物薄膜晶体管的方法

    公开(公告)号：KR1020130113972A

    公开(公告)日：2013-10-16

    申请号：KR1020130017100

    申请日：2013-02-18

    Applicant: 한국전자통신연구원

    Inventor： 박상희 ,  유민기 ,  오힘찬 ,  황치선

    IPC: H01L29/786 ,  H01L21/336 ,  G02F1/136 ,  H01L51/50

    CPC classification number: H01L29/66742 ,  H01L27/3258 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/7869

    Abstract: PURPOSE: A method for manufacturing an oxide thin film transistor is provided to improve barrier characteristics by including an etch stop layer. CONSTITUTION: A gate electrode is formed on a substrate. A gate insulating layer is formed on the front surface of the substrate. An oxide semiconductor layer (140) is formed on the gate insulating layer. A first etch stop layer (150) is formed on the oxide semiconductor layer. A second etch stop layer (160) is formed on the first etch stop layer.

    Abstract translation: 目的：提供一种用于制造氧化物薄膜晶体管的方法，以通过包括蚀刻停止层来改善阻挡特性。 构成：在基板上形成栅电极。 栅极绝缘层形成在基板的前表面上。 在栅极绝缘层上形成氧化物半导体层（140）。 在氧化物半导体层上形成第一蚀刻停止层（150）。 在第一蚀刻停止层上形成第二蚀刻停止层（160）。

    산화물 반도체 형성방법
    6.
    发明公开
    산화물 반도체 형성방법 审中-实审
    形成氧化物半导体的方法

    公开(公告)号：KR1020150100088A

    公开(公告)日：2015-09-02

    申请号：KR1020140021441

    申请日：2014-02-24

    Applicant: 한국전자통신연구원

    Inventor： 오힘찬 ,  황치선 ,  양종헌 ,  추혜용

    IPC: H01L21/324 ,  H01L21/316

    CPC classification number: H01L21/324 ,  H01L21/28008

    Abstract: 본 발명은 산화물 반도체 형성방법을 제공한다. 이 산화물 반도체 형성방법은 반응기 내에 용매를 채우는 것, 상기 반응기에 산화물반도체막이 형성된 기판을 넣는 것, 및 상기 반응기를 가열하여 상기 산화물반도체막을 용매열처리하는 것을 포함할 수 있다.

    Abstract translation: 本发明提供一种形成氧化物半导体的方法。 形成氧化物半导体的方法可以包括以下步骤：用溶剂填充反应器; 将具有氧化物半导体层的衬底插入反应器中; 并通过加热反应器对氧化物半导体层进行溶剂热处理。

    트렌지스터 제조방법
    7.
    发明公开
    트렌지스터 제조방법 审中-实审
    制造晶体管的方法

    公开(公告)号：KR1020140080589A

    公开(公告)日：2014-07-01

    申请号：KR1020120144277

    申请日：2012-12-12

    Applicant: 한국전자통신연구원

    Inventor： 오힘찬 ,  황치선

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

    Abstract: A transistor according to an embodiment of the present invention includes source/drain electrodes on a substrate, a semiconductor layer which is interposed between the source/drain electrodes on the substrate, a reducing prevention layer which is arranged on the semiconductor layer, and a gate electrode which is arranged in a region corresponding to the semiconductor layer. The semiconductor layer includes a first semiconductor oxide layer. The source/drain electrodes include the same element as a first oxide semiconductor layer. The source/drain electrodes include a second semiconductor oxide having a lower oxygen content ratio. The transistor has improved reliability and operates with high speed.

    Abstract translation: 根据本发明实施例的晶体管包括衬底上的源/漏电极，介于衬底上的源/漏电极之间的半导体层，布置在半导体层上的还原防止层，以及栅极 电极，其布置在与半导体层对应的区域中。 半导体层包括第一半导体氧化物层。 源极/漏极包括与第一氧化物半导体层相同的元件。 源极/漏极包括具有较低氧含量比的第二半导体氧化物。 晶体管具有改进的可靠性并以高速运行。

    빛과 전압 스트레스에 강한 산화물 박막 트랜지스터 및 그의 제조 방법
    8.
    发明公开
    빛과 전압 스트레스에 강한 산화물 박막 트랜지스터 및 그의 제조 방법 审中-实审
    非常稳定的薄膜晶体管在偏置和照明应力下的制造方法

    公开(公告)号：KR1020120127166A

    公开(公告)日：2012-11-21

    申请号：KR1020110094568

    申请日：2011-09-20

    Applicant: 한국전자통신연구원

    Inventor： 오힘찬 ,  박상희 ,  황치선 ,  유민기

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/78606

    Abstract: PURPOSE: An oxide thin film transistor and a manufacturing method thereof are provided to improve reliability of a photovoltage by forming a diffusion preventing layer which prevents a hole and an ionized oxygen vacancy from moving in a low temperature of 50°C-200°C. CONSTITUTION: A gate electrode(20) is formed on a substrate(10). A gate insulating layer(30) is formed on the upper side of the substrate including the gate electrode. A source electrode(40a) and a drain electrode(40b) are formed on both sides of the gate insulating layer. An active layer(50) and a protective layer(60) are formed on the top of the substrate including a part of the drain electrode and the source electrode. The active layer comprises an oxide semiconductor and a diffusion preventing layer.

    Abstract translation: 目的：提供一种氧化物薄膜晶体管及其制造方法，以通过形成防止空穴和电离氧空位在50℃-200℃的低温下移动的扩散防止层来提高光电压的可靠性。 构成：在基板（10）上形成栅电极（20）。 在包括栅电极的基板的上侧形成栅极绝缘层（30）。 源极电极（40a）和漏电极（40b）形成在栅极绝缘层的两侧。 在包括漏电极和源电极的一部分的衬底的顶部上形成有源层（50）和保护层（60）。 有源层包括氧化物半导体和扩散防止层。

    인버터, ＮＡＮＤ 게이트 및 ＮＯＲ 게이트
    9.
    发明公开
    인버터, ＮＡＮＤ 게이트 및 ＮＯＲ 게이트 有权
    逆变器，NAND门和NOR门

    公开(公告)号：KR1020120108894A

    公开(公告)日：2012-10-05

    申请号：KR1020110085561

    申请日：2011-08-26

    Applicant: 한국전자통신연구원 ,  건국대학교 산학협력단

    Inventor： 박상희 ,  황치선 ,  윤성민 ,  오힘찬 ,  박기찬 ,  임도 ,  임홍균 ,  오민우 ,  김지선 ,  피재은 ,  김병훈 ,  유병곤

    IPC: H03K19/094 ,  H03K19/20

    CPC classification number: H03K19/094 ,  H03K19/00 ,  H03K19/02 ,  H03K19/08 ,  H03K19/20

    Abstract: PURPOSE: An inverter, an NAND gate, and an NOR gate are provided to provide a digital logic gate driven in low consumption power equal to power in a CMOS(Complementary Metal-Oxide Semiconductor) circuit by controlling the flow of a current according to an input and output signal. CONSTITUTION: An inverter comprises a pull-up part(210), a pull down part(220), and a pull up drive part(230). The pull-up part is composed of a second TFT(Thin Film Transistor) outputting a first power supply voltage to an output terminal according to a voltage applied to a gate. The pull down part is composed of a fifth TFT outputting a ground voltage to the output terminal according to the input signal voltage applied to the gate. The pull up drive part applies a second power supply voltage or the ground voltage to the gage in a second TFT according to the input signal.

    Abstract translation: 目的：提供一个反相器，一个与非门和一个或非门，以通过控制电流的流动来提供在CMOS（互补金属氧化物半导体）电路中等于功率的低功耗驱动的数字逻辑门 输入和输出信号。 构成：逆变器包括上拉部分（210），下拉部分（220）和上拉驱动部分（230）。 上拉部分由根据施加到栅极的电压将第一电源电压输出到输出端的第二TFT（薄膜晶体管）组成。 下拉部分由根据施加到栅极的输入信号电压向输出端输出接地电压的第五TFT组成。 上拉驱动部件根据输入信号将第二电源电压或接地电压施加到第二TFT中的量规。

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