公开(公告)号：KR100834412B1

公开(公告)日：2008-06-04

申请号：KR1020070050015

申请日：2007-05-23

Applicant: 한국전자통신연구원

Inventor： 여준기 ,  양일석 ,  허세완 ,  여순일 ,  노태문 ,  김종대 ,  김기철 ,  유세훈

IPC: G06F9/38 ,  G06F15/76

CPC classification number: G06F15/8007

Abstract: A parallel processor for processing a mobile multimedia operation efficiently is provided to reduce a hardware cost and power consumption while providing a flexible structure for easily developing a parallel algorithm related to the multimedia operation, connect with a memory directly, include additional support for a floating point operation, and realize an operation feature of a partitioned SIMD(Single Instruction Multiple Data) and condition execution. A processor array(120) comprises a plurality of PEs(Processing Element). A local memory(110) is directly connected to the processor array. A floating point accumulator array(130) comprises a plurality of accumulators for accelerating floating point addition by connecting to the processor array. A control unit(140) broadcasts an instruction to all PEs of the processor array by reading the instruction from an external memory, and applies an address to the local memory when the PE communicates with the local memory. The PE includes an I/O(Input/Output) port exchanging data with the neighboring PEs, a function unit performing arithmetic/logical operations, a register file storing an operator inputted to the function unit and storing an operation result of the function unit, and an instruction decoder controlling each component by interpreting the instruction received from the control unit.

Abstract translation: 提供了一种用于有效处理移动多媒体操作的并行处理器，以降低硬件成本和功耗，同时提供一种灵活的结构，便于开发与多媒体操作相关的并行算法，直接与存储器连接，包括对浮点的附加支持 操作，实现分区SIMD（单指令多数据）和条件执行的操作特性。 处理器阵列（120）包括多个PE（处理元件）。 本地存储器（110）直接连接到处理器阵列。 浮点累加器阵列（130）包括用于通过连接到处理器阵列来加速浮点加法的多个累加器。 控制单元（140）通过读取来自外部存储器的指令向处理器阵列的所有PE广播指令，并且当PE与本地存储器通信时，向本地存储器应用地址。 PE包括与相邻PE交换数据的I / O（输入/输出）端口，执行算术/逻辑操作的功能单元，存储输入到功能单元的操作者的存储器文件，并存储功能单元的操作结果， 以及通过解释从控制单元接收的指令来控制每个组件的指令解码器。