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    다중처리기 시스템에서의 ISAM 장애해결 방법
    1.
    发明授权
    다중처리기 시스템에서의 ISAM 장애해결 방법 失效
    如何解决多处理器系统中的ISAM故障

    公开(公告)号：KR1019920001966B1

    公开(公告)日：1992-03-07

    申请号：KR1019890019672

    申请日：1989-12-27

    Applicant: 한국전자통신연구원

    Inventor： 정인철 ,  홍동권 ,  임정온 ,  김정숙

    IPC: G06F13/00

    Abstract: The method allows the buffer to be cleaned at interrupt signal due to timeout or a complex state during execution of indexed sequential access method (ISAM). In the case of locking file during updating process between two processors, an abort clean up file is executed to closing the locked file after deleting the data processing structure so that the buffer is to be cleaned for the next operation.

    Abstract translation: 该方法允许在执行索引顺序访问方法（ISAM）期间由于超时或复杂状态而在中断信号处清除缓冲区。 在两个处理器之间的更新处理期间锁定文件的情况下，在删除数据处理结构之后执行中止清理文件以关闭锁定的文件，以便清除缓冲器以进行下一个操作。

    스누우프 제어기의 콘트롤러
    5.
    发明授权
    스누우프 제어기의 콘트롤러 失效
    多处理器系统

    公开(公告)号：KR1019920009442B1

    公开(公告)日：1992-10-16

    申请号：KR1019900021864

    申请日：1990-12-26

    Applicant: 한국전자통신연구원

    Inventor： 함종식 ,  원철호 ,  한우종 ,  전금석 ,  윤용호 ,  임정온

    IPC: G06F13/12

    Abstract: The snoop controller generates control signal necessary for cache coherence protocol according to address signals related to memory cycle within one period of timer pulse. The controller includes a write address comparators (2-5) for comparing bus address signal with write back address signal detected at every rising edge of control signal to generate write address match signal, read address comparators (10-13) for comparing bus address signal with read address signal detected at every vising edge of timing pulses to generate read address match signal, a first program enable memory (15) for generating bus parity error signal and acting signal according to bus address space signal, bus address enable signal, and snoop action stop signal, a second program enable memory (16) for generating write back going signal and a third program enable memory (17) for generating state memory write enable signal and data input signal.

    Abstract translation: 侦听控制器根据与定时器脉冲的一个周期内的存储器周期相关的地址信号，产生高速缓存一致性协议所需的控制信号。 控制器包括用于比较总线地址信号和在控制信号的每个上升沿检测到的回写地址信号以产生写入地址匹配信号的写入地址比较器（2-5），用于比较总线地址信号的读取地址比较器（10-13） 具有在定时脉冲的每个边缘处检测到读取地址信号以产生读取地址匹配信号;第一编程使能存储器（15），用于根据总线地址空间信号，总线地址使能信号和窥探产生总线奇偶校验错误信号和作用信号 动作停止信号，用于产生回写信号的第二程序使能存储器（16）和用于产生状态存储器写使能信号和数据输入信号的第三程序使能存储器（17）。

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