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公开(公告)号：KR1020120070993A
公开(公告)日：2012-07-02
申请号：KR1020100132560
申请日：2010-12-22
Applicant: 한국전자통신연구원 , 서울대학교산학협력단
CPC classification number: H04W72/046 , H04B7/0413 , H04L27/26 , H04W72/08
Abstract: PURPOSE: A resource allocation method of an E-node B and an apparatus thereof in a multiple user MIMO-OFDMA system is provided to increase transmission efficiency by properly allocating a resource in a channel environment. CONSTITUTION: An E-node B allocates UEs(User Equipments) to each sub carrier in one or more types(400). The E-node B calculates transmission power based on information related to a space path(402). The E-node B stores sum of data rate if the calculated transmission power is the maximum transmission power(406). The E-node B selects total sum in a resource assignment algorithm(409).
Abstract translation: 目的：提供多用户MIMO-OFDMA系统中的E节点B的资源分配方法及其装置，通过在信道环境中适当分配资源来提高传输效率。 构成：E节点B以一种或多种类型（400）为每个子载波分配UE（用户设备）。 E节点B基于与空间路径相关的信息来计算发送功率（402）。 如果所计算的发送功率是最大发送功率，则E节点B存储数据速率的总和（406）。 E节点B在资源分配算法（409）中选择总和。
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公开(公告)号：KR1020140114793A
公开(公告)日：2014-09-29
申请号：KR1020140031702
申请日：2014-03-18
Applicant: 서울대학교산학협력단
IPC: H04B7/14
CPC classification number: H04B7/15585 , H04B7/15528
Abstract: A repeater in a bidirectional transfer relay network according to one embodiment of the present invention includes a repeater reception antenna which simultaneously receives a signal from two terminals which want to transmit/receive a signal with each other, a repeater control part which deletes a loop interference signal based on incomplete channel information in a signal received from the repeater reception antenna, and a repeater transmission/reception antenna which transmits an amplified signal to the two terminals.
Abstract translation: 根据本发明的一个实施例的双向传送中继网络中的中继器包括：中继器接收天线，其同时从两个终端接收希望彼此发送/接收信号的信号;中继器控制部分，其删除环路干扰 基于从中继器接收天线接收的信号中的不完整信道信息的信号，以及向两个终端发送放大信号的中继器发送/接收天线。
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公开(公告)号：KR1020100027926A
公开(公告)日：2010-03-11
申请号：KR1020080103381
申请日：2008-10-22
Applicant: 엘지전자 주식회사 , 서울대학교산학협력단
CPC classification number: H04B7/026
Abstract: PURPOSE: A method of allocating resources for cooperative diversity is provided to guarantee QoS(Quality of Service) of a fixed level for each user while improving a data transmission rate of the entire system. CONSTITUTION: Channel conditions about each source station are obtained(S610). One or more subcarriers are exclusively allocated to each source station based on the channel conditions. A relay station about each source station is selected(S620). Cooperative diversity is performed using the same subcarrier as a source station to which the relay station corresponds. The subcarrier is assigned to satisfy a minimum data rate necessary for each source station for service quality satisfaction of a user.
Abstract translation: 目的：提供一种分配资源以进行协同分集的方法，以保证每个用户固定级别的QoS（服务质量），同时提高整个系统的数据传输速率。 构成：获得关于每个源站的信道条件（S610）。 基于信道条件将一个或多个子载波专门分配给每个源站。 选择关于每个源站的中继站（S620）。 使用与中继站对应的源站相同的子载波来执行协同分集。 分配子载波以满足每个源站对用户的服务质量满意度所需的最小数据速率。
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公开(公告)号：KR101509098B1
公开(公告)日：2015-04-08
申请号：KR1020140031702
申请日：2014-03-18
Applicant: 서울대학교산학협력단
IPC: H04B7/14
Abstract: 본발명의실시예에따른양방향전이중중계네트워크에서의중계기는상호간에신호의송수신을원하는두 개의단말기로부터동시에신호를수신하는중계기수신안테나, 상기중계기수신안테나로수신된신호에서불완전채널정보에기초하여루프간섭신호를제거하고, 증폭하는중계기제어부및 증폭된신호된신호를상기두 개의단말기로전송하는중계기송신안테나를포함한다.
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公开(公告)号：KR101523098B1
公开(公告)日：2015-05-28
申请号：KR1020080103381
申请日：2008-10-22
Applicant: 엘지전자 주식회사 , 서울대학교산학협력단
Abstract: 무선통신시스템에서협력다이버시티를위한자원할당방법은복수의소스국과복수의중계국에대한채널상태를획득하는단계, 및상기채널상태를기반으로하여각 소스국에배타적으로적어도하나의부반송파를할당하고, 각소스국에대한중계국을선택하는단계를포함한다. 상기중계국은대응하는소스국과동일한부반송파를이용하여협력다이버시티를수행한다.
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Patent Agency Ranking
公开(公告)号：KR1019950022421A
公开(公告)日：1995-07-28
申请号：KR1019930029082
申请日：1993-12-22
Applicant: 한국전자통신연구원
IPC: H04L12/40
Abstract: 본 발명은 데이타 배열위치가 상이한 두 버스 사이의 마스터측 전송제어장치에 관한 것으로서, 프로세서에서 구동된 제어신호들을 버스의 사용권을 얻기 전에 VME64 버스용 제어신호로 미리 변환하기 위한 신호변환기(13)와, 상기 변환된 제어신호들을 이용하여 적당한 시점에 적당한 위치의 버퍼를 적당한 방향으로 선택적으로 구동하는 제어신호를 발생하는 전송제어기(14)와, 전송제어기에서 발생한 제어신호를 이용하여 데이타를 데이타 버스에 직접 구동하기 위한 양방향 데이타 버퍼(8, 9, 10)와, VME64 버스(17)에 있는 특정자원을 지정하여 억세스하기 위한 어드레스 버퍼(11)로 구성되고, 프로세서 제어신호를 VME64 버스쪽의 제어신호들로 변환하기 위한 제2 디코더(20)와, 데이타 전송을 위한 신호들의 타이밍을 VME64 버스규격에 맞추면서 제어신호의 변 시간으로 지연이 발생하지 않게하고, 시간차 구동을 실현하기 위한 전송시점제어기(18) 및 제1디코더(19)와, 상기 버퍼구동신호를 발생하기 위한 제3 디코더(21)와, 전송완료 신호를 구동하여 통신제어기(7)에서 보내온 안정된 데이타를 시스템 제어기의 프로세서가 받도록 하기 위한 전송완료 지연로직(22)으로 구성되어 인텔계열의 프로세서를 사용하는 시스템으로서 로우컬버스와 VME64 버스 사이의 데이타 전송 프로토콜의 차이를 극복하고, 정확한 데이타 전송을 실현할 수 있다.
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公开(公告)号：KR1019960009665B1
公开(公告)日：1996-07-23
申请号：KR1019930029084
申请日：1993-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: a signal converter(8) for generating firsttr* and scndtr* signals which indicate a number of transmissions if a data is larger than port sizes or does not aligned to a port size width when accessing to 4 byte or 2 byte port communication controller; a state controller(9) for controlling transmitting time using dtack*, berr*, vmbreq*, and vmbgr* signals; a decoder for generating a transmission ending signal(ldtack*) and an error signal(lberr*) using Tout[3:0 (transmitting starting time control signal), vmiack*, be*[7:0 , and r/w signals, and driving buffer in a certain direction; and buffers for data transmission.
Abstract translation: 信号转换器（8），用于在访问4字节或2字节端口通信控制器时产生指示传输数量如果数据大于端口大小或不与端口大小宽度对齐的第一传输和/或传输信号; 用于使用dtack *，berr *，vmbreq *和vmbgr *信号控制发送时间的状态控制器（9） 使用Tout [3：0（发送开始时间控制信号），vmiack *，be * [7：0和r / w信号]生成发送结束信号（ldtack *）和错误信号（lberr *）的解码器， 和行驶缓冲区在一定方向; 和缓冲区用于数据传输。
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公开(公告)号：KR1019960009470B1
公开(公告)日：1996-07-19
申请号：KR1019930029346
申请日：1993-12-23
Applicant: 한국전자통신연구원
IPC: H04L12/40
Abstract: The controller includes a data transmission path consisting of bidirectional data buffers(8,9,10) and address buffer(11), and address counters(12,13) and counter address buffers(14,15), a third decoder(28) for generating signals for controlling the buffers, and a second decoder(23) for generating signals for controlling the effective time point of data reading and writing, determining the driving point of the bidirectional data buffers(14,15), latching the initial address, increasing the address, driving clock input of counters(24,26), and driving buffers(25,27) of the address counters(24,26) when an address driving is required.
Abstract translation: 控制器包括由双向数据缓冲器（8,9,10）和地址缓冲器（11），以及地址计数器（12,13）和计数器地址缓冲器（14,15）组成的数据传输路径，第三解码器（28） 用于产生用于控制缓冲器的信号;以及第二解码器（23），用于产生用于控制数据读取和写入的有效时间点的信号，确定双向数据缓冲器（14,15）的驱动点，锁存初始地址， 当需要地址驱动时，增加地址，驱动计数器（24,26）的时钟输入和地址计数器（24,26）的驱动缓冲器（25,27）。
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公开(公告)号：KR1019960009469B1
公开(公告)日：1996-07-19
申请号：KR1019930029082
申请日：1993-12-22
Applicant: 한국전자통신연구원
IPC: H04L12/40
CPC classification number: F25B2400/02
Abstract: The transmission controller includes a second decoder(20) for converting a processor control signal into a control signal of VME64 bus side, a transmission time point controller(18) and first decoder(19) for performing time difference driving, a third decoder(21) for generating a buffer driving signal to selectively latch-enable buffers(8,9,10), and a transmission completion delay(22) for driving a transmission completion signal when a predetermined period of time passes after transmission data is latched by the buffers(8,9,10), to allow the processor of a system controller(5) to receive stable data transmitted from a communication controller(7).
Abstract translation: 传输控制器包括用于将处理器控制信号转换成VME64总线侧的控制信号的第二解码器（20），用于执行时差驱动的传输时间点控制器（18）和第一解码器（19），第三解码器 ），用于产生用于选择性地锁存使能缓冲器（8,9,10）的缓冲器驱动信号和用于当在由缓冲器锁存发送数据之后经过预定时间段时驱动发送完成信号的发送完成延迟（22） （8,9,10），以允许系统控制器（5）的处理器接收从通信控制器（7）发送的稳定数据。
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