Abstract:
A comparator capable of realizing a stabilized output signal is disclosed. A latch type comparator senses a difference of input signals in the positive edge of a clock signal and forms a first set signal and a first reset signal. A buffer part is included in order to stabilize the output level of the formed first set signal and first reset signal and enhance the drive efficiency of a device. A second set signal and a second reset signal are formed through a buffering operation and are inputted to a latch part with an expended swing width. A stabilized output range is secured by the forementioned. [Reference numerals] (100) Latch type comparator;(200) Buffer part;(300) Latch part
Abstract:
Disclosed is a reference voltage generator which forms a constant output voltage even in a temperature change. The reference voltage generator has a reference voltage generation part which generates a reference voltage by the generation of a reference current and a start-up control part which induces the start-up operation of the reference voltage generation part. The start-up control part is connected to a temperature correction part which induces the generation of a constant reference current even in a temperature change. Especially, the start-up control part receives both terminal voltages of a detection resistance which is connected in series to the bipolar transistor of the temperature correction part and induces the start-up operation of the reference voltage generation part based on a received signal. Therefore, the start-up operation can be carried out by accurately detecting the operation condition of the temperature correction part which performs a temperature correction operation.
Abstract:
샘플링 정확도를 증가시키기 위한 스위칭 회로를 적용시킨 시그마-델타 아날로그-디지털 컨버터가 개시된다. 시그마-델타 방식의 아날로그-디지털 컨버터에 사용되는 스위치드-커패시터(switched capacitor) 적분기는 샘플링 클럭에 따라 스위치드-커패시터 적분기의 샘플링 동작(sampling phase)을 스위칭 하는 제1 스위칭 회로; 적분 클럭에 따라 스위치드-커패시터 적분기의 적분 동작(integration phase)을 스위칭 하는 제2 스위칭 회로; 및 리셋 클럭에 따라 스위치드-커패시터 적분기의 리셋 동작(reset phase)을 스위칭 하는 제3 스위칭 회로를 포함할 수 있다.
Abstract:
PURPOSE: A sigma-delta analog-digital converter is provided to increase overall resolution. CONSTITUTION: An operational amplifier(10) connects an input terminal to a fourth node(D) and connects an output terminal to an output end. A sampling capacitor(20) connects one end to a second node, connects the other end to a third node and samples. An integral capacitor(30) connects one end to the fourth node, connects the other end to an output terminal of the operational amplifier and feedbacks. A first switching circuit(40) switches sampling operation of a switched-capacitor integrator according to a sampling clock. A second switching circuit(50) switches integration operation of the switched-capacitor integrator according to an integration clock. A third switching circuit(70) switches reset operation of the switched-capacitor integrator according to a reset clock.