-
公开(公告)号：AU2003275208A1
公开(公告)日：2004-04-19
申请号：AU2003275208
申请日：2003-09-24
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： SATOU SADANOBU , KIMURA TERUHIKO , GORRELL ROBIN E , SYLVESTER MARK F , BANKS DONALD R , HOLCOMB MICHAEL D , BALLARD WILLIAM V , HIROSAWA KOUICHI
IPC: H01L23/498
Abstract: A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.
-
公开(公告)号：SG185566A1
公开(公告)日：2012-12-28
申请号：SG2012083721
申请日：2011-05-06
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： PALANISWAMY RAVI , TAN FONG LIANG , IMKEN RONALD L , GORRELL ROBIN E
IPC: B31B50/62
Abstract: Provided is a means of improving the adhesion between a flexible circuit coverfilm and an encapsulant material in an inkjet printer application.
-
公开(公告)号：AU2003294307A1
公开(公告)日：2004-06-18
申请号：AU2003294307
申请日：2003-11-18
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： HOLCOMB MICHAEL D , BALLARD WILLIAM V , SYLVESTER MARK F , SCHILDGEN WILLIAM R , GORRELL ROBIN E
IPC: H01L23/498 , H05K1/02 , H05K3/46
Abstract: An interconnect module providing conductive interconnection paths between an integrated chip, a printed wiring board, and at least one layer within the module, incorporating a plurality of alternating dielectric and conductive layers laminated together to form a unitary structure. The module includes a chip attach surface and a board attach surface, that define contact pads for attachment to corresponding pads on the chip and printed wiring board, respectively, by means of solder balls.
-
公开(公告)号：AU2003275208A8
公开(公告)日：2004-04-19
申请号：AU2003275208
申请日：2003-09-24
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： GORRELL ROBIN E , KIMURA TERUHIKO , BANKS DONALD R , BALLARD WILLIAM V , SYLVESTER MARK F , SATOU SADANOBU , HIROSAWA KOUICHI , HOLCOMB MICHAEL D
IPC: H01L23/498
Abstract: A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.
-
公开(公告)号：WO2016109168A3
公开(公告)日：2016-10-27
申请号：PCT/US2015065504
申请日：2015-12-14
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： GABRIEL NICHOLAS T , JESME RONALD D , OUDERKIRK ANDREW J , PALANISWAMY RAVI , BONIFAS ANDREW P , NARAG ALEJANDRO ALDRIN A II , JENNINGS ROBERT M , GORRELL ROBIN E
CPC classification number: H05K1/0283 , G06K19/025 , H01Q1/2225 , H01Q1/36 , H05K1/165 , H05K2201/09263 , H05K2201/09272 , H05K2201/09727 , H05K2201/09736 , H05K2201/10098
Abstract: Electrical conductors are disclosed. More particularly, undulating electrical conductors 110 are disclosed. The conductors have varying width and a varying radius of curvature along the length of the conductor. The conductor comprises alternating first locations 114 and second locations 116 such that the conductor at each first location is wider than at each second location. Certain disclosed electrical conductors may be suitable to be disposed on flexible or stretchable substrates.
Abstract translation: 公开了电导体。 更具体地，公开了起伏的电导体110。 导体具有沿着导体长度的变化的宽度和变化的曲率半径。 导体包括交替的第一位置114和第二位置116，使得在每个第一位置处的导体比在每个第二位置处的导体宽。 某些公开的电导体可以适于设置在柔性或可拉伸的基底上。
-
Patent Agency Ranking
公开(公告)号：WO2014081917A2
公开(公告)日：2014-05-30
申请号：PCT/US2013071187
申请日：2013-11-21
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： GHOSH DIPANKAR , LYONS CHRISTOPHER S , GORRELL ROBIN E , MAKI STEPHEN P
IPC: H01G4/33
CPC classification number: H01G4/33 , H01G4/20 , H01G4/206 , H01L28/56 , H05K1/036 , H05K1/0393 , H05K1/162 , H05K3/022 , H05K2201/0179 , H05K2201/0195 , H05K2203/1366
Abstract: A multilayer dielectric film including a first dielectric layer made from a material having a first breakdown field strength and a second dielectric layer disposed on the first dielectric layer made from a material having a different breakdown filed strength. A multilayer film including a first electrically conductive layer, the first dielectric layer disposed on the first electrically conductive layer, the second dielectric layer disposed on the first dielectric layer, and a second electrically conductive layer disposed on the second dielectric layer is also disclosed. The first electrically conductive layer can have at least one of an average surface roughness of at least ten nanometers, a thickness of at least ten micrometers, or an average visible light transmission of up to ten percent. The first dielectric layer may be a polymer and typically has a lower dielectric constant than the second dielectric layer, which may be ceramic.
Abstract translation: 一种多层电介质膜，包括由具有第一击穿场强的材料制成的第一电介质层和设置在具有不同击穿场强的材料制成的第一电介质层上的第二电介质层。 还公开了一种多层膜，其包括第一导电层，设置在第一导电层上的第一介电层，设置在第一介电层上的第二介电层和设置在第二介电层上的第二导电层。 第一导电层可以具有至少10纳米的平均表面粗糙度，至少10微米的厚度或高达10％的平均可见光透射率中的至少一个。 第一介电层可以是聚合物，并且通常具有比可以是陶瓷的第二介电层更低的介电常数。
-
公开(公告)号：WO2014081918A3
公开(公告)日：2014-11-06
申请号：PCT/US2013071192
申请日：2013-11-21
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： GHOSH DIPANKAR , LYONS CHRISTOPHER S , GORRELL ROBIN E , MAKI STEPHEN P
CPC classification number: H01G4/10 , C23C14/083 , C23C14/34 , C23C16/22 , C23C28/32 , C23C28/3455 , C25D5/00 , H01G4/20 , H01G4/206 , H01G4/33 , H01L28/56 , H05K1/0393 , H05K1/162 , H05K3/022 , H05K3/4655 , H05K2203/1545
Abstract: A multilayer dielectric film including a first dielectric layer made from a material having a first breakdown field strength and a second dielectric layer disposed on the first dielectric layer made from a material having a different breakdown filed strength. A multilayer film including first and second electrically conductive layers separated by at least first and second dielectric layers is also disclosed. The first dielectric layer is disposed on the first electrically conductive layer, and the second dielectric layer is disposed on the first dielectric layer. The first electrically conductive layer can have at least one of an average surface roughness of at least ten nanometers, a thickness of at least ten micrometers, or an average visible light transmission of up to ten percent. The first dielectric layer may be a polymer and typically has a lower dielectric constant than the second dielectric layer, which may be ceramic.
Abstract translation: 一种多层介电膜，包括由具有第一击穿场强度的材料制成的第一介电层和设置在由具有不同击穿场强度的材料制成的第一介电层上的第二介电层。 还公开了包括由至少第一和第二介电层分开的第一和第二导电层的多层膜。 第一电介质层设置在第一导电层上，第二电介质层设置在第一电介质层上。 第一导电层可具有至少十纳米的平均表面粗糙度，至少十微米的厚度或至多百分之十的平均可见光透射率中的至少一个。 第一电介质层可以是聚合物并且通常具有比可以是陶瓷的第二电介质层更低的介电常数。
-
公开(公告)号：WO2016018777A2
公开(公告)日：2016-02-04
申请号：PCT/US2015042171
申请日：2015-07-27
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： GEISSINGER JOHN D , PETERSON DONALD G , GORRELL ROBIN E , KAPLAN HOWARD M
IPC: G06K19/077
CPC classification number: G06K19/07722 , G06K19/025 , G06K19/077 , G06K19/07718 , G06K19/07728 , G06K19/0776 , G06K19/07773 , G06K19/07783 , H01Q1/2225 , H01Q1/36 , H01Q1/38
Abstract: A radio frequency identification (RFID) tag that includes an antenna having a spiral form disposed on a major surface of a flexible substrate is described. The RFID tag includes a first terminal disposed at a first end of the antenna and a second terminal disposed at the second end of the antenna. The RFID tag may include a pad portion along the length of the antenna between the first and second ends for mounting an integrated circuit. Except for the pad portion, a radius of curvature of the antenna along at least 90 percent of a length of the antenna between the first and second ends is greater than about 0.1 mm and less than about 10 mm.
Abstract translation: 描述了包括设置在柔性基板的主表面上的具有螺旋形状的天线的射频识别（RFID）标签。 RFID标签包括设置在天线的第一端的第一终端和设置在天线的第二端的第二终端。 RFID标签可以包括沿着天线的长度在第一和第二端之间的垫部分，用于安装集成电路。 除了焊盘部分之外，天线沿着第一和第二端之间的天线长度的至少90％的曲率半径大于约0.1mm且小于约10mm。
-
公开(公告)号：WO2011146258A3
公开(公告)日：2012-05-10
申请号：PCT/US2011035486
申请日：2011-05-06
Applicant: 3M INNOVATIVE PROPERTIES CO
Inventor： PALANISWAMY RAVI , TAN FONG LIANG , IMKEN RONALD L , GORRELL ROBIN E
CPC classification number: H05K3/28 , B29C59/04 , H05K1/189 , H05K2201/0397 , H05K2201/10674 , H05K2201/10977 , H05K2203/0108 , H05K2203/0143 , H05K2203/1152 , Y10T156/10
Abstract: Provided is a means of improving the adhesion between a flexible circuit coverfilm and an encapsulant material in an inkjet printer application.
Abstract translation: 提供了一种在喷墨打印机应用中改善柔性电路覆盖膜和密封剂材料之间的粘附性的方法。
-
公开(公告)号：WO2004030096A3
公开(公告)日：2004-06-17
申请号：PCT/US0330060
申请日：2003-09-24
Applicant: 3M INNOVATIVE PROPERTIES CO , NEC ELECTRONICS CORP
Inventor： GORRELL ROBIN E , SYLVESTER MARK F , BANKS DONALD R , HOLCOMB MICHAEL D , BALLARD WILLIAM V , HIROSAWA KOUICHI , SATOU SADANOBU , KIMURA TERUHIKO
IPC: H01L23/498
CPC classification number: H01L23/49822 , H01L23/49816 , H01L23/49894 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/01057 , H01L2924/01079 , H01L2924/15311 , H01L2924/16195 , H01L2924/3511
Abstract: A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.
Abstract translation: 一种叠层倒装芯片互连封装，包括具有芯片附着表面和板附着表面的衬底，所述衬底附着表面限定用于附着到所述芯片和板上的相应焊盘的接触焊盘，其中所述衬底板表面包括覆盖所述芯片附着表面的至少一个实体平面 区域靠近至少一个芯片角落。 在一个实施例中，固体平面包括电介质材料，可选地用焊料掩模或覆盖层材料覆盖。 在替代实施例中，固体平面包括金属，可选地用焊料掩模或覆盖层材料覆盖。
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.023 seconds)
