Power semiconductor arrangement
    1.
    发明公开
    Power semiconductor arrangement 审中-公开
    Leistungshalbleiteranordnung

    公开(公告)号:EP2530711A1

    公开(公告)日:2012-12-05

    申请号:EP11168071.6

    申请日:2011-05-30

    CPC classification number: H01L23/62 H01L25/072 H01L2924/0002 H01L2924/00

    Abstract: The present invention relates to a power semiconductor arrangement comprising a power semiconductor device (14), having an emitter electrode and a collector electrode, wherein the collector electrode is electrically connected to a lower electrode (16) and the emitter electrode is electrically connected to an upper electrode (18), wherein the power semiconductor device (14) is arranged to at least one further power semiconductor device in parallel. In order to allow the power semiconductor arrangement (10) to provide an electrical short-circuit mode after a failure event having an improved reliability as well as durability, the arrangement (10) further comprises a high energy material (34) being connected to the power semiconductor device (14) and being connected to at least one failure current bypass unit (36, 54, 70), the failure current bypass unit (36, 54, 70) being arranged in parallel to the power semiconductor device (14) and being activatable by the high energy material (34) to form a current bypass.

    Abstract translation: 本发明涉及一种功率半导体装置,包括具有发射电极和集电极的功率半导体器件(14),其中集电极电连接到下电极(16),并且发射极电连接到 上电极(18),其中所述功率半导体器件(14)被并行布置至至少一个另外的功率半导体器件。 为了允许功率半导体布置(10)在具有改善的可靠性和耐久性的故障事件之后提供电短路模式,所述布置(10)还包括高能材料(34),其连接到 功率半导体器件(14)并且连接到至少一个故障电流旁路单元(36,54,70),故障电流旁路单元(36,54,70)与功率半导体器件(14)并联布置,并且 可由高能材料(34)激活以形成电流旁路。

    Power semiconductor arrangement
    2.
    发明公开
    Power semiconductor arrangement 审中-公开
    功率半导体布置

    公开(公告)号:EP2544229A1

    公开(公告)日:2013-01-09

    申请号:EP11172958.8

    申请日:2011-07-07

    Abstract: The present invention relates to a power semiconductor arrangement (10) comprising a power semiconductor device (12), having an emitter electrode and a collector electrode, wherein the collector electrode is electrically connected to a lower electrode (14) and wherein the emitter electrode is electrically connected to an upper electrode (16), wherein the arrangement (10) further comprises a failure mode contact element (30) and a low temperature melting material (28), the low temperature melting material (28) being arranged between the failure mode contact element (30) and the semiconductor device (12), wherein the failure mode contact element (30) is spring loaded towards the low temperature melting material (28) and comprises at least one contact portion (32) being spaced apart from the lower electrode (14) in a distance being smaller or equal than the thickness of the low temperature melting material (28) in a regular working mode of the power semiconductor arrangement (10). A power semiconductor arrangement (10) according to the invention provides an improved failure mode.

    Abstract translation: 本发明涉及包括具有发射极电极和集电极电极的功率半导体器件(12)的功率半导体装置(10),其中集电极电极电连接到下电极(14),并且其中发射极电极是 (10)还包括故障模式接触元件(30)和低温熔化材料(28),所述低温熔化材料(28)布置在所述故障模式 (30)和所述半导体器件(12),其中所述故障模式接触元件(30)朝向所述低温熔融材料(28)被弹簧加载并且包括至少一个接触部分(32),所述接触部分 在所述功率半导体装置(10)的正常工作模式下,所述电极(14)的距离小于或等于所述低温熔化材料(28)的厚度。 根据本发明的功率半导体装置(10)提供了改进的故障模式。

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