公开(公告)号：US20170294526A1

公开(公告)日：2017-10-12

申请号：US15630491

申请日：2017-06-22

Applicant: ABB Schweiz AG

Inventor： Liutauras Storasta ,  Chiara Corvasce ,  Manuel Le Gallo ,  Munaf Rahimo ,  Arnost Kopta

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/78 ,  H01L29/40 ,  H01L29/36 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7395 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0865 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/7396 ,  H01L29/7811 ,  H01L29/7819 ,  H01L29/7823

Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

公开(公告)号：US10109725B2

公开(公告)日：2018-10-23

申请号：US15630491

申请日：2017-06-22

Applicant: ABB Schweiz AG

Inventor： Liutauras Storasta ,  Chiara Corvasce ,  Manuel Le Gallo ,  Munaf Rahimo ,  Arnost Kopta

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/40 ,  H01L29/08

Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

公开(公告)号：US20180012773A1

公开(公告)日：2018-01-11

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/3213 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L21/32131 ,  H01L21/304 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.

公开(公告)号：US10141196B2

公开(公告)日：2018-11-27

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/00 ,  H01L21/3213 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.

公开(公告)号：US20190109218A1

公开(公告)日：2019-04-11

申请号：US16156457

申请日：2018-10-10

Applicant: ABB Schweiz AG

Inventor： Chiara Corvasce ,  Arnost Kopta ,  Maxi Andenna ,  Munaf Rahimo

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225 ,  H01L21/324 ,  H01L29/66

Abstract: An IGBT is provided comprising at least two first cells (1, 1′), each of which having an n doped source layer (2), a p doped base layer (3), an n doped enhancement layer (4), wherein the base layer (3) separates the source layer (2) from the enhancement layer (4), an n− doped drift layer (5) and a p doped collector layer (6). Two trench gate electrodes (7, 7′) are arranged on the lateral sides of the first cell (1, 1′).The transistor comprises at least one second cell (15) between the trench gate electrodes (7, 7′) of two neighboured first cells (1, 1′), which has on the emitter side (90) a p+ doped well (8) and a further n doped enhancement layer (40, 40′) which separates the well (8) from the neighboured trench gate electrodes (7, 7′). An insulator layer stack (75) is arranged on top of the second cell (15) on the emitter side (90) to insulate the second cell (15) and the neighboured trench gate electrodes (7, 7′) from the metal emitter electrode (9), which consists of a first insulating layer (73) and a second insulating layer (74), wherein the insulator stack (75) has a thickness on top of the well (8) of a first layer thickness plus the second insulating layer thickness and a thickness on top of the gate layer (70, 70′) of the second insulating layer thickness, wherein each thickness of the first insulating layer (73) and the second insulating layer (74) is at least 700 nm.