公开(公告)号：US10141196B2

公开(公告)日：2018-11-27

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/00 ,  H01L21/3213 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.

公开(公告)号：US20190363029A1

公开(公告)日：2019-11-28

申请号：US16531296

申请日：2019-08-05

Applicant: ABB Schweiz AG

Inventor： David Guillon ,  Charalampos Papadopoulos ,  Dominik Truessel ,  Fabian Fischer ,  Samuel Hartmann

IPC: H01L23/053 ,  H01L23/24 ,  H01L23/31 ,  H01L23/00 ,  H01L23/492

Abstract: The present application provides a power semiconductor module, including a support which carries at least one power semiconductor device, the support together with the power semiconductor device is at least partly located in a housing, the support and the power semiconductor device are at least partly covered by a sealing material, additionally to the sealing material, a protecting material is provided in the housing, the protecting material is formed from silicon gel and the protecting material at least partly covers at least one of the support, the power semiconductor device and the sealing material.

公开(公告)号：US20180047652A1

公开(公告)日：2018-02-15

申请号：US15677625

申请日：2017-08-15

Applicant: ABB Schweiz AG

Inventor： Charalampos Papadopoulos ,  Munaf Rahimo

IPC: H01L23/31 ,  H01L29/78 ,  H01L21/02 ,  H01L29/40

Abstract: A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 μm. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.

公开(公告)号：US20180012773A1

公开(公告)日：2018-01-11

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/3213 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L21/32131 ,  H01L21/304 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.

公开(公告)号：US10854524B2

公开(公告)日：2020-12-01

申请号：US16531296

申请日：2019-08-05

Applicant: ABB Schweiz AG

Inventor： David Guillon ,  Charalampos Papadopoulos ,  Dominik Truessel ,  Fabian Fischer ,  Samuel Hartmann

IPC: H01L23/053 ,  H01L23/24 ,  H01L23/31 ,  H01L23/492 ,  H01L23/00

Abstract: The present application provides a power semiconductor module, including a support which carries at least one power semiconductor device, the support together with the power semiconductor device is at least partly located in a housing, the support and the power semiconductor device are at least partly covered by a sealing material, additionally to the sealing material, a protecting material is provided in the housing, the protecting material is formed from silicon gel and the protecting material at least partly covers at least one of the support, the power semiconductor device and the sealing material.

公开(公告)号：US10468321B2

公开(公告)日：2019-11-05

申请号：US15677625

申请日：2017-08-15

Applicant: ABB Schweiz AG

Inventor： Charalampos Papadopoulos ,  Munaf Rahimo

IPC: H01L23/31 ,  H01L21/02 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861 ,  H01L29/16

Abstract: A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 μm. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.