公开(公告)号：US20180012773A1

公开(公告)日：2018-01-11

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/3213 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L21/32131 ,  H01L21/304 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.

公开(公告)号：US10249499B2

公开(公告)日：2019-04-02

申请号：US15459099

申请日：2017-03-15

Applicant: ABB SCHWEIZ AG

Inventor： Wolfgang Janisch ,  Atze de Vries ,  Sven Matthias

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/20 ,  H01L29/66 ,  H01L29/739 ,  H01L21/762 ,  H01L29/744 ,  H01L21/283 ,  H01L21/673 ,  H01L29/08

Abstract: A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.

公开(公告)号：US10141196B2

公开(公告)日：2018-11-27

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/00 ,  H01L21/3213 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.