公开(公告)号：US10141196B2

公开(公告)日：2018-11-27

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/00 ,  H01L21/3213 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.

公开(公告)号：US20190123172A1

公开(公告)日：2019-04-25

申请号：US16157435

申请日：2018-10-11

Applicant: ABB Schweiz AG

Inventor： Luca De-Michielis ,  Chiara Corvasce

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

Abstract: An insulated gate power semiconductor device includes an (n−) doped drift layer between an emitter side and a collector side. A p doped protection pillow covers a trench bottom of a trench gate electrode. An n doped enhancement layer having a maximum enhancement layer doping concentration in an enhancement layer depth separates the base layer from the drift layer. An n doped plasma enhancement layer having a maximum plasma enhancement layer doping concentration covers an edge region between the protection pillow and the trench gate electrode. The n doping concentration decreases from the maximum enhancement layer doping concentration towards the plasma enhancement layer and the n doping concentration decreases from the maximum plasma enhancement layer doping concentration towards the enhancement layer such that the n doping concentration has a local doping concentration minimum between the enhancement layer and the plasma enhancement layer.

公开(公告)号：US10128361B2

公开(公告)日：2018-11-13

申请号：US15661631

申请日：2017-07-27

Applicant: ABB Schweiz AG

Inventor： Luca De-Michielis ,  Chiara Corvasce

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L21/225

Abstract: An insulated gate power semiconductor device has an (n−) doped drift layer between an emitter side and a collector side. A trench gate electrode has a trench bottom and trench lateral sides and extends to a trench depth. A p doped first protection pillow covers the trench bottom. An n doped second protection pillow encircles the trench gate electrode at its trench lateral sides. The second protection pillow has a maximum doping concentration in a first depth, which is at least half the trench depth, wherein a doping concentration of the second protection pillow decreases towards the emitter side from the maximum doping concentration to a value of not more than half the maximum doping concentration. An n doped enhancement layer has a maximum doping concentration in a second depth, which is lower than the first depth, wherein the doping concentration has a local doping concentration minimum between the second depth and the first depth.

公开(公告)号：US20170323959A1

公开(公告)日：2017-11-09

申请号：US15661631

申请日：2017-07-27

Applicant: ABB Schweiz AG

Inventor： Luca De-Michielis ,  Chiara Corvasce

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/7397 ,  H01L21/2253 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/66348

Abstract: An insulated gate power semiconductor device has an (n−) doped drift layer between an emitter side and a collector side. A trench gate electrode has a trench bottom and trench lateral sides and extends to a trench depth. A p doped first protection pillow covers the trench bottom. An n doped second protection pillow encircles the trench gate electrode at its trench lateral sides. The second protection pillow has a maximum doping concentration in a first depth, which is at least half the trench depth, wherein a doping concentration of the second protection pillow decreases towards the emitter side from the maximum doping concentration to a value of not more than half the maximum doping concentration. An n doped enhancement layer has a maximum doping concentration in a second depth, which is lower than the first depth, wherein the doping concentration has a local doping concentration minimum between the second depth and the first depth.

公开(公告)号：US20170294526A1

公开(公告)日：2017-10-12

申请号：US15630491

申请日：2017-06-22

Applicant: ABB Schweiz AG

Inventor： Liutauras Storasta ,  Chiara Corvasce ,  Manuel Le Gallo ,  Munaf Rahimo ,  Arnost Kopta

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/78 ,  H01L29/40 ,  H01L29/36 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7395 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0865 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/7396 ,  H01L29/7811 ,  H01L29/7819 ,  H01L29/7823

Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

公开(公告)号：US09553086B2

公开(公告)日：2017-01-24

申请号：US15191295

申请日：2016-06-23

Applicant: ABB Schweiz AG

Inventor： Liutauras Storasta ,  Chiara Corvasce ,  Manuel Le-Gallo ,  Munaf Rahimo

IPC: H01L29/74 ,  H01L27/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L27/0635 ,  H01L27/0727 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/417 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7397

Abstract: A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

Abstract translation: 一种反向导电半导体器件，其包括在公共晶片上的续流二极管和绝缘栅双极晶体管，其中的一部分晶片形成具有第一掺杂浓度和基底层厚度的第一导电类型的基极层。 绝缘栅双极晶体管包括与晶片的集电极侧相对的集电极侧和发射极侧。 具有至少一个第一区域的第一导电类型的阴极层和具有至少一个第二引导区域和第二导电区域的第二导电类型的阳极层交替地布置在集电极侧。 每个区域具有由区域边界包围的区域宽度的区域区域。 本申请的反向导通IGBT满足若干具体的几何规则。

公开(公告)号：US20160307888A1

公开(公告)日：2016-10-20

申请号：US15191295

申请日：2016-06-23

Applicant: ABB Schweiz AG

Inventor： Liutauras Storasta ,  Chiara Corvasce ,  Manuel Le-Gallo ,  Munaf Rahimo

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L27/0635 ,  H01L27/0727 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/417 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7397

Abstract: A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

Abstract translation: 一种反向导电半导体器件，其包括在公共晶片上的续流二极管和绝缘栅双极晶体管，其中的一部分晶片形成具有第一掺杂浓度和基底层厚度的第一导电类型的基极层。 绝缘栅双极晶体管包括与晶片的集电极侧相对的集电极侧和发射极侧。 具有至少一个第一区域的第一导电类型的阴极层和具有至少一个第二引导区域和第二导电区域的第二导电类型的阳极层在集电极侧交替布置。 每个区域具有由区域边界包围的区域宽度的区域区域。 本申请的反向导通IGBT满足若干具体的几何规则。

公开(公告)号：US20190109218A1

公开(公告)日：2019-04-11

申请号：US16156457

申请日：2018-10-10

Applicant: ABB Schweiz AG

Inventor： Chiara Corvasce ,  Arnost Kopta ,  Maxi Andenna ,  Munaf Rahimo

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225 ,  H01L21/324 ,  H01L29/66

Abstract: An IGBT is provided comprising at least two first cells (1, 1′), each of which having an n doped source layer (2), a p doped base layer (3), an n doped enhancement layer (4), wherein the base layer (3) separates the source layer (2) from the enhancement layer (4), an n− doped drift layer (5) and a p doped collector layer (6). Two trench gate electrodes (7, 7′) are arranged on the lateral sides of the first cell (1, 1′).The transistor comprises at least one second cell (15) between the trench gate electrodes (7, 7′) of two neighboured first cells (1, 1′), which has on the emitter side (90) a p+ doped well (8) and a further n doped enhancement layer (40, 40′) which separates the well (8) from the neighboured trench gate electrodes (7, 7′). An insulator layer stack (75) is arranged on top of the second cell (15) on the emitter side (90) to insulate the second cell (15) and the neighboured trench gate electrodes (7, 7′) from the metal emitter electrode (9), which consists of a first insulating layer (73) and a second insulating layer (74), wherein the insulator stack (75) has a thickness on top of the well (8) of a first layer thickness plus the second insulating layer thickness and a thickness on top of the gate layer (70, 70′) of the second insulating layer thickness, wherein each thickness of the first insulating layer (73) and the second insulating layer (74) is at least 700 nm.

公开(公告)号：US10109725B2

公开(公告)日：2018-10-23

申请号：US15630491

申请日：2017-06-22

Applicant: ABB Schweiz AG

Inventor： Liutauras Storasta ,  Chiara Corvasce ,  Manuel Le Gallo ,  Munaf Rahimo ,  Arnost Kopta

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/40 ,  H01L29/08

Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

公开(公告)号：US20180012773A1

公开(公告)日：2018-01-11

申请号：US15714094

申请日：2017-09-25

Applicant: ABB Schweiz AG

Inventor： Sven Matthias ,  Charalampos Papadopoulos ,  Chiara Corvasce ,  Arnost Kopta

IPC: H01L21/3213 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L21/32131 ,  H01L21/304 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.