公开(公告)号：EP3435543A1

公开(公告)日：2019-01-30

申请号：EP17460046.0

申请日：2017-07-27

Applicant: ABB Schweiz AG

Inventor： Jacukowicz, Rafal ,  Kopta, Arnost

IPC: H03K17/082 ,  H03K17/18 ,  H03K17/14 ,  H03K17/08

Abstract: A semiconductor device (1) including a power switch packaging (3) and a gate control unit (2) connected together. The power switch packaging (3) includes semiconductor power switch (4) equipped with current terminals (C, E) and a switch control terminal (G). The power switch packaging (3) includes an auxiliary circuit (5) that is equipped with a sensor (6). The sensor (6) is adapted for measuring physical parameters of the semiconductor power switch (4) and for transforming the physical parameters into electrical signal S. The sensor (6) is connected in series with a transmitter circuit (7) for transmitting electrical signal S to the gate control unit (2). The transmitter circuit (7) is connected in series with a power supply circuit (8) adapted for harvesting electrical energy for supplying the auxiliary circuit (5).

公开(公告)号：EP3240040A1

公开(公告)日：2017-11-01

申请号：EP16167002.1

申请日：2016-04-26

Applicant: ABB Schweiz AG

Inventor： Kopta, Arnost ,  Corvasce, Chiara ,  Rahimo, Munaf ,  Matthias, Sven ,  Janisch, Wolfgang

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66348

Abstract: An insulated gate bipolar is produced, wherein the following steps are performed:
(a) providing a lowly n doped substrate (1) having an emitter side (20) and a collector side (27),
(b) forming n and p doped layers on the emitter side (20),
(c) thinning the substrate (1) on the collector side (27),
(d) implanting an n first dopant (82) on the collector side (27) into a depth of at most 2 µm,
(e) forming a first buffer layer (8) by annealing the first dopant (82),
(f) applying a surface layer comprising an n second dopant on top of the collector side (27),
(g) forming a second buffer layer (9) by annealing the second dopant, wherein the second buffer layer (9) having a lower maximum doping concentration than the first buffer layer (8),
(h) applying a p third dopant at the collector side (27),
(i) forming a collector layer (6) by annealing the third dopant.

Abstract translation: 制造绝缘栅双极型，其中执行以下步骤：（a）提供具有发射极侧（20）和集电极侧（27）的低n型掺杂衬底（1），（b）形成n和p掺杂层 在发射极侧（20）上，（c）在集电极侧（27）上使衬底（1）变薄，（d）在集电极侧（27）注入n型第一掺杂剂（82），深度至多为2 （e）通过退火所述第一掺杂剂（82）形成第一缓冲层（8），（f）在所述集电极侧（27）的顶部上施加包含n第二掺杂剂的表面层，（g）形成第二缓冲层 其中所述第二缓冲层（9）具有比所述第一缓冲层（8）更低的最大掺杂浓度，（h）在所述集电极侧（27）施加第三掺杂剂，（ i）通过退火第三掺杂剂形成集电极层（6）。