公开(公告)号：WO2008005083A1

公开(公告)日：2008-01-10

申请号：PCT/US2007/007842

申请日：2007-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  MICHAEL, Mark, W. ,  CHEN, Jian

Inventor： MICHAEL, Mark, W. ,  CHEN, Jian

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/823418 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method includes forming a plurality of functional features (210, 410) on a semiconductor layer (205, 405) in a first region. A non-functional feature (240, 415) corresponding to the functional feature (210, 410) is formed adjacent at least one of the functional features (210, 410) disposed on a periphery of the region. A stress- inducing layer (300, 500) is formed proximate the functional features (210, 410) and the non-functional feature (240, 415). A device (200, 400) includes a semiconductor layer (205, 405), a plurality of transistor elements (210, 410), a first dummy gate electrode (240A, 415A), and a stress-inducing layer (300, 500). The plurality of transistor elements (210, 410) is formed above the semiconductor layer (205, 405). The plurality includes at least a first end transistor element (210A, 410A), a second end transistor element (210D, 410C), and at least one interior transistor element (210B, 21 OC, 410B). The first dummy gate electrode (240A, 415A) is disposed proximate the first end transistor element (210A, 415A). The stress-inducing layer (300, 500) is disposed proximate the plurality of transistor elements (210, 410) and the first dummy gate electrode (240A, 415A).

Abstract translation: 一种方法包括在第一区域中的半导体层（205,405）上形成多个功能特征（210,410）。 对应于功能特征（210,410）的非功能特征（240,415）形成在邻近设置在区域外围的功能特征（210,410）中的至少一个功能特征（210,410）。 在功能特征（210,410）和非功能特征（240,415）附近形成应力诱导层（300,500）。 一种器件（200,400）包括半导体层（205,405），多个晶体管元件（210,410），第一伪栅电极（240A，415A）和应力诱导层（300,500） 。 多个晶体管元件（210,410）形成在半导体层（205,405）的上方。 多个至少包括第一端部晶体管元件（210A，410A），第二端部晶体管元件（210D，410C）和至少一个内部晶体管元件（210B，21C，410B）。 第一虚拟栅电极（240A，415A）设置在第一端部晶体管元件（210A，415A）附近。 应力诱导层（300,500）设置在多个晶体管元件（210,410）和第一伪栅电极（240A，415A）附近。

公开(公告)号：WO1997027633A1

公开(公告)日：1997-07-31

申请号：PCT/US1996017412

申请日：1996-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHEN, Jian

IPC: H01L29/861

CPC classification number: H01L29/861 ,  G11C16/02 ,  G11C16/0416 ,  H01L27/115 ,  H01L29/8616

Abstract: A floating gate diode which can be used as a sourceless memory cell, and which may be arranged into an array of memory cells is disclosed. The floating gate diode comprises: a drain region (64) formed in a substrate (62); an oxide overlying and associated with the drain region (64); and a floating gate (66) overlying the oxide. Upon application of a voltage to the drain (64), a current between the drain (64) and substrate (62) is induced in proportion to an amount of electrons stored on the gate. The cells may be arranged into an array which comprises a substrate having a surface; a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate; an oxide region overlying the plurality of drain regions on the surface of the substrate; and a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions.

Abstract translation: 公开了可以用作无源存储器单元并且可以被布置成存储器单元阵列的浮置栅极二极管。 浮栅二极管包括：形成在衬底（62）中的漏区（64）; 覆盖并与漏区（64）相连的氧化物; 和覆盖氧化物的浮动栅极（66）。 在向漏极（64）施加电压时，与存储在栅极上的电子量成比例地引起漏极（64）和衬底（62）之间的电流。 电池可以被布置成包括具有表面的衬底的阵列; 多个漏极区，分别对应于所述多个单元中的一个的所述漏极区中的一个，形成在所述衬底中; 覆盖所述基板的表面上的所述多个漏极区域的氧化物区域; 以及覆盖所述氧化物并且分别与所述多个漏极区域相关联的多个浮动栅极。

公开(公告)号：WO1997047047A1

公开(公告)日：1997-12-11

申请号：PCT/US1997003229

申请日：1997-02-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HSU, James ,  CHEN, Jian ,  TANG, Yuan

IPC: H01L29/788

CPC classification number: H01L29/66825

Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

Abstract translation: 公开了一种用于提供具有双漫射植入结的非常短的通道存储单元的系统和方法。 该系统和方法包括提供结植入物（110），提供间隔物（108）以及提供双漫射植入物（112）的顺序步骤。 由于在间隔物之后提供双漫射植入物，所以双漫射植入物在处理之后不会延伸到存储单元的栅极之下。 因此，存储器单元具有基本上不缩短通道的有效长度的分级结。 因此，存储器单元可以随着存储器单元的尺寸减小而起作用。 此外，双漫射植入物的热循环可以与结植入物的热循环去耦合。 这是在没有使处理复杂化的情况下实现的。 因此，整体系统性能得到提高。

公开(公告)号：EP0934602A1

公开(公告)日：1999-08-11

申请号：EP97907966.0

申请日：1997-02-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HSU, James ,  CHEN, Jian ,  TANG, Yuan

IPC: H01L21

CPC classification number: H01L29/66825

Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

公开(公告)号：EP0934602B1

公开(公告)日：2004-01-02

申请号：EP97907966.2

申请日：1997-02-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HSU, James ,  CHEN, Jian ,  TANG, Yuan

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66825

Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.