公开(公告)号：WO1997003470A1

公开(公告)日：1997-01-30

申请号：PCT/US1996010698

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HSU, James ,  LONGCOR, Steven, W.

IPC: H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/11534

Abstract: An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of a different width, which may be optimized for different voltage requirements, are formed along the gates of a second type of transistor of the same intergated circuit. This method is particularly applicable in the formation of EPROM, Flash EPROM, EEPROM, or other memory cells in conjunction with periphery devices needing to sustain relatively higher voltages. By decoupling the memory cell requirement from the periphery device requirement, tighter gate spacing and smaller cell size can be achieved.

Abstract translation: 公开了一种用于保护半导体器件的栅极边缘和相邻源极区域的改进方法。 在这种方法中，沿着一种类型的晶体管的栅极形成间隔物，以在自对准源蚀刻期间保护栅极边缘和相邻源极区。 沿着相同的间隔电路的第二类型的晶体管的栅极形成不同宽度的间隔，其可以针对不同的电压要求进行优化。 该方法特别适用于与需要维持相对较高电压的周边设备相结合的EPROM，闪存EPROM，EEPROM或其它存储单元的形成。 通过将存储单元需求与外围设备要求相结合，可以实现更紧密的门间距和更小的单元大小。

公开(公告)号：WO1997047047A1

公开(公告)日：1997-12-11

申请号：PCT/US1997003229

申请日：1997-02-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HSU, James ,  CHEN, Jian ,  TANG, Yuan

IPC: H01L29/788

CPC classification number: H01L29/66825

Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

Abstract translation: 公开了一种用于提供具有双漫射植入结的非常短的通道存储单元的系统和方法。 该系统和方法包括提供结植入物（110），提供间隔物（108）以及提供双漫射植入物（112）的顺序步骤。 由于在间隔物之后提供双漫射植入物，所以双漫射植入物在处理之后不会延伸到存储单元的栅极之下。 因此，存储器单元具有基本上不缩短通道的有效长度的分级结。 因此，存储器单元可以随着存储器单元的尺寸减小而起作用。 此外，双漫射植入物的热循环可以与结植入物的热循环去耦合。 这是在没有使处理复杂化的情况下实现的。 因此，整体系统性能得到提高。

公开(公告)号：EP0934602B1

公开(公告)日：2004-01-02

申请号：EP97907966.2

申请日：1997-02-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HSU, James ,  CHEN, Jian ,  TANG, Yuan

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66825

Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

公开(公告)号：EP0934602A1

公开(公告)日：1999-08-11

申请号：EP97907966.0

申请日：1997-02-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HSU, James ,  CHEN, Jian ,  TANG, Yuan

IPC: H01L21

CPC classification number: H01L29/66825

Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

公开(公告)号：EP0780023B1

公开(公告)日：2002-04-10

申请号：EP96922531.7

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HSU, James ,  LONGCOR, Steven, W.

IPC: H01L27/115 ,  H01L27/105 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/11534

Abstract: An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of a different width, which may be optimized for different voltage requirements, are formed along the gates of a second type of transistor of the same intergated circuit. This method is particularly applicable in the formation of EPROM, Flash EPROM, EEPROM, or other memory cells in conjunction with periphery devices needing to sustain relatively higher voltages. By decoupling the memory cell requirement from the periphery device requirement, tighter gate spacing and smaller cell size can be achieved.

公开(公告)号：EP0780023A1

公开(公告)日：1997-06-25

申请号：EP96922531.0

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HSU, James ,  LONGCOR, Steven, W.

IPC: H01L21 ,  H01L27 ,  H01L29

CPC classification number: H01L27/11526 ,  H01L27/11534

Abstract: An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of a different width, which may be optimized for different voltage requirements, are formed along the gates of a second type of transistor of the same intergated circuit. This method is particularly applicable in the formation of EPROM, Flash EPROM, EEPROM, or other memory cells in conjunction with periphery devices needing to sustain relatively higher voltages. By decoupling the memory cell requirement from the periphery device requirement, tighter gate spacing and smaller cell size can be achieved.