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    MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
    2.
    发明申请
    MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE 审中-公开
    带有金属硅化物线的MONOS器件

    公开(公告)号：WO2003054964A2

    公开(公告)日：2003-07-03

    申请号：PCT/US2002/039781

    申请日：2002-12-11

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： OGURA, Jusuke ,  RAMSBEY, Mark, T. ,  HALLIYAL, Arvind ,  KRIVOKAPIC, Zoran ,  NGO, Minh, Van ,  TRIPSAS, Nicholas, H.

    IPC: H01L27/115

    CPC classification number: H01L27/11568 ,  H01L21/743 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    Abstract: A MONOS device and method for making the device has a charge trapping dielectric layer (32), such as an oxide-nitride-oxide (ONO) layer (34, 36, 38), formed on a substrate (30). A recess (44) is created through the ONO layer (32) and in the substrate (30). A metal silicide bit line (48) is formed in the recess (44) and bit line oxide (54) is formed on top of the metal silicide. A word line (56) is formed over the ONO layer (32) and the bit line oxide (54), and a low resistance silicide (58) is provided on top of the word line (56). The silicide (58) is formed by laser thermal annealing, for example.

    Abstract translation: 用于制造该器件的MONOS器件和方法具有形成在衬底（30）上的电荷捕获介电层（32），例如氧化物 - 氮化物 - 氧化物（ONO）层（34,36,38）。 通过ONO层（32）和衬底（30）产生凹陷（44）。 金属硅化物位线（48）形成在凹槽（44）中，位线氧化物（54）形成在金属硅化物的顶部。 在ONO层（32）和位线氧化物（54）之上形成字线（56），并且在字线（56）的顶部设置低电阻硅化物（58）。 硅化物（58）例如由激光热退火形成。

    DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY
    4.
    发明申请
    DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY 审中-公开
    SONOS闪存中的双密密封门

    公开(公告)号：WO2003032393A2

    公开(公告)日：2003-04-17

    申请号：PCT/US2002/031330

    申请日：2002-09-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： SUN, Yu ,  VAN BUSKIRK, Michael, A. ,  RAMSBEY, Mark, T.

    IPC: H01L27/105

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric (114) over a substrate (112); forming a first set of memory cell gates (116) over the charge trapping dielectric (114) in a core region; forming a conformal insulation material layer (118) around the first set of memory cell gates (116); and forming a second set of memory cell gates (122) in the core region, wherein each memory cell gate of the second set of memory cell gates (122) is adjacent to at least one memory cell gate of the first set of memory cell gates (116), each memory cell gate of the first set of memory cell gates (116) is adjacent at least one memory cell gate of the second set of memory cell gates (122), and the conformal insulation material layer (118) is positioned between each adjacent memory cell gate is disclosed.

    Abstract translation: 一种形成非易失性半导体存储器件的方法，包括在衬底（112）上方形成电荷俘获电介质（114）; 在核心区域中的所述电荷俘获电介质（114）上方形成第一组存储器单元栅极（116） 围绕所述第一组存储器单元栅极（116）形成共形绝缘材料层（118）; 以及在核心区域中形成第二组存储器单元栅极（122），其中第二组存储器单元栅极（122）中的每一存储器单元栅极与第一组存储器单元栅极（122）中的至少一个存储器单元栅极相邻 （116）中，所述第一组存储器单元栅极（116）的每个存储器单元栅极与所述第二组存储器单元栅极（122）中的至少一个存储器单元栅极相邻，并且所述共形绝缘材料层（118）被定位 在每个相邻的存储单元门之间被公开。

    ESD IMPLANT FOLLOWING SPACER DEPOSITION
    5.
    发明申请
    ESD IMPLANT FOLLOWING SPACER DEPOSITION 审中-公开

    公开(公告)号：WO2003003460A3

    公开(公告)日：2003-01-09

    申请号：PCT/US2001/049056

    申请日：2001-12-14

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： RAMSBEY, Mark, T. ,  FLIESLER, Michael ,  RANDOLPH, Mark ,  QIAN, Mimi ,  SUN, Yu

    IPC: H01L27/02

    Abstract: One aspect of the present invention provides a process for forming IC devices (100) with ESD protection transistors (112). According to one aspect of the invention, an ESD protection transistor (112) is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors (112) that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device (100).

    ISOLATION OF SONOS DEVICES
    7.
    发明申请
    ISOLATION OF SONOS DEVICES 审中-公开
    SONOS设备的隔离

    公开(公告)号：WO2003003451A1

    公开(公告)日：2003-01-09

    申请号：PCT/US2001/049047

    申请日：2001-12-14

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： YANG, Jean, Yee-Mei ,  RAMSBEY, Mark, T. ,  LINGUNIS, Emmanuil, Manos ,  WU, Yider ,  KAMAL, Tazrien ,  HE, Yi ,  HSIA, Edward ,  SHIRAIWA, Hidehiko

    IPC: H01L21/8246

    CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L27/11568 ,  H01L29/66833

    Abstract: One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

    Abstract translation: 本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷捕获电介质的第三层（如果存在） 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷捕获电介质的第三层（如果存在） 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或 在电荷俘获电介质的第三层上形成附加材料。

    POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL
    8.
    发明申请
    POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL 审中-公开
    用于补充位冲突改进和SONOS存储单元充电改进的POCKET IMPLAN

    公开(公告)号：WO2005078791A1

    公开(公告)日：2005-08-25

    申请号：PCT/US2004/042855

    申请日：2004-12-17

    Applicant: ADVANCED MICRO DEVICES, INC. ,  LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

    Inventor： LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

    IPC: H01L21/8246

    CPC classification number: H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

    Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

    Abstract translation: 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 最初，电荷俘获电介质层（608）的一部分形成在衬底（602）上，并且在电荷俘获电介质层（608）的部分上形成抗蚀剂（614）。 对抗蚀剂（614）进行图案化，并且以一定角度执行凹穴注入（630）以在衬底（602）内建立凹穴注入（620）。 然后执行位线植入（634）以在衬底（602）内建立掩埋位线（640）。 然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层（608）。 字线材料（660）形成在电荷俘获电介质层的剩余部分上并被图案化以形成覆盖在位线（640）上的字线（662）。 口袋植入物（620）用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。 因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

    HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
    10.
    发明申请
    HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS 审中-公开
    用于存储器件的硬掩模工艺，不含任何短路

    公开(公告)号：WO2003079446A1

    公开(公告)日：2003-09-25

    申请号：PCT/US2003/001855

    申请日：2003-01-21

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： YANG, Jean, Y. ,  RAMSBEY, Mark, T. ,  SHIRAIWA, Hidehiko ,  WU, Yider ,  LINGUNIS, Emmanuil ,  KAMAL, Tazrien

    IPC: H01L27/112

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate [102] [602] and depositing a charge-trapping dielectric layer [504] [606]. First and second bitlines [512] [608] are implanted and a wordline layer [515] is deposited [610]. A hard mask layer [516] is deposited over the wordline layer [515] [612]. The hard mask layer [516] is of a material formulated for removal without damaging the charge-trapping dielectric layer [504]. A photoresist [518] is deposited over the wordline layer [515] and used to form a hard mask [519] [618]. The photoresist [518] is removed [620]. The wordline layer [515] is processed using the hard mask [519] to form a wordline [525-528].

    Abstract translation: 用于MirrorBit闪存的制造方法包括提供半导体衬底[102]和沉积电荷俘获介电层[504] [606]。 植入第一和第二位线[512] [608]，并且存储字线层[515] [610]。 硬掩模层[516]沉积在字线层[515] [612]上。 硬掩模层[516]是配制用于去除而不损坏电荷捕获电介质层的材料[504]。 光刻胶[518]沉积在字线层[515]上并用于形成硬掩模[618]。 [620]去除光致抗蚀剂[620]。 使用硬掩模[519]处理字线层[515]以形成字线[525-528]。

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