公开(公告)号：WO2005038810A1

公开(公告)日：2005-04-28

申请号：PCT/US2004/030415

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

Abstract translation: 存储单元阵列（50）包括制造在半导体衬底（54）上的存储单元（52）的二维阵列。 存储单元（52）被布置成限定行方向（67）和限定列方向（69）的多列的多行。 每列存储单元（52）包括多个交替沟道区（58）和源/漏区（64）。 导电互连（72）位于每个源/漏区（64）上方并且仅耦合到另一个源极/漏极区（64）。 另一个源极/漏极区域（64）位于与该列相邻的第二列中。 导电互连（64）被定位成使得每隔一个导电互连（64）连接到列的右侧的相邻列，并且每隔一个导电互连连接到列的左侧的相邻列。 多个源极/漏极控制线（70）在相邻列的存储器单元（52）之间延伸并且电耦合到在相邻列之间耦合的每个导电互连（72）。

公开(公告)号：WO2003003460A3

公开(公告)日：2003-01-09

申请号：PCT/US2001/049056

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  FLIESLER, Michael ,  RANDOLPH, Mark ,  QIAN, Mimi ,  SUN, Yu

IPC: H01L27/02

Abstract: One aspect of the present invention provides a process for forming IC devices (100) with ESD protection transistors (112). According to one aspect of the invention, an ESD protection transistor (112) is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors (112) that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device (100).

公开(公告)号：WO2005038933A1

公开(公告)日：2005-04-28

申请号：PCT/US2004/030696

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  ZHENG, Wei ,  RANDOLPH, Mark

Inventor： ZHENG, Wei ,  RANDOLPH, Mark

IPC: H01L29/788

CPC classification number: H01L29/42336 ,  H01L29/7883 ,  H01L29/792

Abstract: A memory cell with reduced short channel effects is described. A source region (54) and a drain region (56) are formed in a semiconductor substrate (58). A trench region (59) is formed between the source region and the drain region. A recessed channel region (52) is formed below the trench region, the source region and the drain region. A gate dielectric layer (60) is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer (70) is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer.

Abstract translation: 描述了具有减小的短通道效应的存储单元。 在半导体衬底（58）中形成源区（54）和漏区（56）。 在源极区域和漏极区域之间形成沟槽区域（59）。 在沟槽区域，源极区域和漏极区域的下方形成凹陷沟道区域（52）。 栅极电介质层（60）形成在半导体衬底的沟槽区域中的凹陷沟道区域之上和源极区域与漏极区域之间。 在半导体衬底上形成控制栅极层（70），该沟道区域在凹槽沟槽区域上方，其中控制栅极层通过栅极介电层与凹陷沟道区域分离。

公开(公告)号：WO2003003460A2

公开(公告)日：2003-01-09

申请号：PCT/US2001/049056

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  FLIESLER, Michael ,  RANDOLPH, Mark ,  QIAN, Mimi ,  SUN, Yu

IPC: H01L27/02

CPC classification number: H01L29/7833 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the present invention provides a process for forming IC devices (100) with ESD protection transistors (112). According to one aspect of the invention, an ESD protection transistor (112) is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors (112) that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device (100).

Abstract translation: 本发明的一个方面提供一种用于形成具有ESD保护晶体管（112）的IC器件（100）的工艺。 根据本发明的一个方面，ESD保护晶体管（112）具有轻掺杂，然后在形成间隔物之后进行重掺杂。 具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。 因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管（112）。 间隔物可以与其它晶体管的间隔物同时形成，例如器件（100）的外围区域中的其它晶体管。

公开(公告)号：WO2003001601A2

公开(公告)日：2003-01-03

申请号：PCT/US2001/048825

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  DERHACOBIAN, Narbeh ,  WANG, Janet ,  HUI, Angela ,  PHAM, Tuan ,  SUNKAVALLI, Ravi ,  RANDOLPH, Mark

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: One aspect of the present invention relates to a method of forming spacers (56) in a SONOS type nonvolatile semiconductor memory device, involving providing a substrate (40) having a core region (42) and periphery region (44), the core region (42) containing SONOS type memory cells (48) and the periphery region (44) containing gate transistors (50); implanting a first implant into the core region (42) and a first implant into the perifery region (44) of the substrate (40); forming a spacer material (52) over the substrate (40); masking the core region (42) and forming spacers (56) adjacent the gate transistors (50) in the perifery region (44); and implanting a second implant into the perifery region (44) of the substrate (40).

Abstract translation: 本发明的一个方面涉及一种在SONOS型非易失性半导体存储器件中形成间隔物（56）的方法，包括提供具有芯区（42）和周边区（44）的基底（40），芯区（ 42），包含SONOS型存储单元（48）和包含栅极晶体管（50）的外围区域（44）; 将第一植入物植入所述芯区域（42）中并将第一植入物植入所述基底（40）的所述外围区域（44）中; 在衬底（40）上形成间隔物（52）; 掩蔽所述芯区域（42）并在所述外形区域（44）中形成与所述栅极晶体管（50）相邻的间隔物（56）。 以及将第二植入物植入到所述基底（40）的外围区域（44）中。

公开(公告)号：EP1064679A1

公开(公告)日：2001-01-03

申请号：EP98963265.8

申请日：1998-12-17

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED ,  Fujitsu AMD Semiconductor Limited

Inventor： CHEN, Hung-Sheng ,  KIM, Unsoon ,  SUN, Yu ,  CHANG, Chi ,  RAMSBEY, Mark ,  RANDOLPH, Mark ,  KAJITA, Tatsuya ,  HUI, Angela ,  WANG, Fei ,  CHANG, Mark

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

公开(公告)号：EP1673781B1

公开(公告)日：2007-07-25

申请号：EP04784309.9

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

公开(公告)号：EP1673781A1

公开(公告)日：2006-06-28

申请号：EP04784309.9

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.