中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.024 seconds)

    HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
    1.
    发明申请
    HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS 审中-公开
    用于存储器件的硬掩模工艺，不含任何短路

    公开(公告)号：WO2003079446A1

    公开(公告)日：2003-09-25

    申请号：PCT/US2003/001855

    申请日：2003-01-21

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： YANG, Jean, Y. ,  RAMSBEY, Mark, T. ,  SHIRAIWA, Hidehiko ,  WU, Yider ,  LINGUNIS, Emmanuil ,  KAMAL, Tazrien

    IPC: H01L27/112

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate [102] [602] and depositing a charge-trapping dielectric layer [504] [606]. First and second bitlines [512] [608] are implanted and a wordline layer [515] is deposited [610]. A hard mask layer [516] is deposited over the wordline layer [515] [612]. The hard mask layer [516] is of a material formulated for removal without damaging the charge-trapping dielectric layer [504]. A photoresist [518] is deposited over the wordline layer [515] and used to form a hard mask [519] [618]. The photoresist [518] is removed [620]. The wordline layer [515] is processed using the hard mask [519] to form a wordline [525-528].

    Abstract translation: 用于MirrorBit闪存的制造方法包括提供半导体衬底[102]和沉积电荷俘获介电层[504] [606]。 植入第一和第二位线[512] [608]，并且存储字线层[515] [610]。 硬掩模层[516]沉积在字线层[515] [612]上。 硬掩模层[516]是配制用于去除而不损坏电荷捕获电介质层的材料[504]。 光刻胶[518]沉积在字线层[515]上并用于形成硬掩模[618]。 [620]去除光致抗蚀剂[620]。 使用硬掩模[519]处理字线层[515]以形成字线[525-528]。

    FLASH MEMORY DEVICE
    2.
    发明申请
    FLASH MEMORY DEVICE 审中-公开
    闪存存储器件

    公开(公告)号：WO2005062310A1

    公开(公告)日：2005-07-07

    申请号：PCT/US2004/035482

    申请日：2004-10-26

    Applicant: ADVANCED MICRO DEVICES, INC. ,  HILL, Wiley, Eugene ,  WANG, Haihong ,  WU, Yider ,  YU, Bin

    Inventor： HILL, Wiley, Eugene ,  WANG, Haihong ,  WU, Yider ,  YU, Bin

    IPC: G11C16/04

    CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

    Abstract: A memory device (100) includes a conductive structure (210), a number of dielectric layers (410­430) and a control gate (510). The dielectric layers (410-430) are formed around the conductive structure (210) and the control gate (510) is formed over the dielectric layers (410-430). A portion of the conductive structure (210) functions as a drain region (1005) for the memory device (100) and at least one of the dielectric layers (410-430) functions as a charge storage structure for the memory device (100). The dielectric layers (410-430) may include oxide-nitride-oxide layers.

    Abstract translation: 存储器件（100）包括导电结构（210），多个电介质层（410430）和控制栅极（510）。 电介质层（410-430）围绕导电结构（210）形成，并且控制栅极（510）形成在电介质层（410-430）上。 导电结构（210）的一部分用作存储器件（100）的漏极区（1005），并且介电层（410-430）中的至少一个用作存储器件（100）的电荷存储结构。 。 电介质层（410-430）可以包括氧化物 - 氮化物 - 氧化物层。

    ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH
    3.
    发明申请
    ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH 审中-公开
    双点虚拟地面闪存的擦除方法

    公开(公告)号：WO2003001530A2

    公开(公告)日：2003-01-03

    申请号：PCT/US2002/007641

    申请日：2002-03-14

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： HAMILTON, Darlene, G. ,  TANPAIROJ, Kulachet ,  WU, Yider

    IPC: G11C

    CPC classification number: G11C16/16 ,  G11C16/0475 ,  G11C16/0491

    Abstract: A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells (10, 82, 84, 86, 88) in a memory device, such as a flash memory. Each of the dual bits (10, 82, 84, 86, 88) has a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.

    Abstract translation: 提供了一种系统和方法来验证擦除存储器设备（例如闪存）中的一个或多个双位虚拟接地存储器单元（10,82,84,86,88）。 双位（10,82,84,86,88）中的每一个具有与第一或正常位相关联的第一或正常位和第二或补充位。 系统和方法包括验证和擦除单元的正常位和互补位。 擦除包括将一组擦除脉冲施加到单个双位单元中的正常位和补充位。 该组擦除脉冲由单元或晶体管结中的位的两侧的双面擦除脉冲组成，之后是一侧的第一单侧擦除脉冲和到晶体管结的另一侧的第二单侧擦除脉冲 。

    ISOLATION OF SONOS DEVICES
    5.
    发明申请
    ISOLATION OF SONOS DEVICES 审中-公开
    SONOS设备的隔离

    公开(公告)号：WO2003003451A1

    公开(公告)日：2003-01-09

    申请号：PCT/US2001/049047

    申请日：2001-12-14

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： YANG, Jean, Yee-Mei ,  RAMSBEY, Mark, T. ,  LINGUNIS, Emmanuil, Manos ,  WU, Yider ,  KAMAL, Tazrien ,  HE, Yi ,  HSIA, Edward ,  SHIRAIWA, Hidehiko

    IPC: H01L21/8246

    CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L27/11568 ,  H01L29/66833

    Abstract: One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

    Abstract translation: 本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷捕获电介质的第三层（如果存在） 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷捕获电介质的第三层（如果存在） 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或 在电荷俘获电介质的第三层上形成附加材料。

    MANUFACTURE OF SEMICONDUCTOR DEVICE WITH SPACING NARROWER THAN LITHOGRAPHY LIMIT
    7.
    发明申请
    MANUFACTURE OF SEMICONDUCTOR DEVICE WITH SPACING NARROWER THAN LITHOGRAPHY LIMIT 审中-公开
    半导体器件的制造与间距NARROWER超过刻画限制

    公开(公告)号：WO2003030230A1

    公开(公告)日：2003-04-10

    申请号：PCT/US2002/013578

    申请日：2002-04-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： WU, Yider ,  KIM, UnSoon ,  SUN, Yu ,  YANG, Jean, Yee-Mei

    IPC: H01L21/033

    CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/11517

    Abstract: A method for transferring a reduced lithographic image size pattern onto a film (14) on a substrate (12) is disclosed. A photosensitive material having an opening (20) of a minimum size achievable by the limits of lithography is transferred onto a mask layer (16) on a substrate (12) having a film (14) thereon. Reduction in the image size is achieved by establishing sidewalls (28) to the interior vertical surfaces (26) of the opening of the mask layer (16) by depositing a conformal layer (28), followed by anisotropic etching. The dimension of the opening (24) is reduced by the combined thickness of the two opposite sidewalls (28). An anisotropic etching of the film (14) transfers a pattern of openings (30) of a minimum size smaller than possible by lithography.

    Abstract translation: 公开了一种将还原的平版印刷图像尺寸图案转印到基片（12）上的薄膜（14）上的方法。 具有通过光刻限制可实现的最小尺寸的开口（20）的感光材料被转印到其上具有膜（14）的基底（12）上的掩模层（16）上。 通过沉积保形层（28），然后进行各向异性蚀刻，通过将掩模层（16）的开口的内部垂直表面（26）建立侧壁（28）来实现图像尺寸的减小。 开口（24）的尺寸减小了两个相对侧壁（28）的组合厚度。 薄膜（14）的各向异性蚀刻通过光刻传递尺寸小于可能的最小尺寸的开口（30）图案。

    ISOLATION OF SONOS DEVICES
    9.
    发明公开
    ISOLATION OF SONOS DEVICES 有权
    SONOS零件的绝缘

    公开(公告)号：EP1399965A1

    公开(公告)日：2004-03-24

    申请号：EP01996286.9

    申请日：2001-12-14

    Applicant: Advanced Micro Devices, Inc. ,  Fujitsu Limited

    Inventor： YANG, Jean, Yee-Mei ,  RAMSBEY, Mark, T. ,  LINGUNIS, Emmanuil, Manos ,  WU, Yider ,  KAMAL, Tazrien ,  HE, Yi ,  HSIA, Edward ,  SHIRAIWA, Hidehiko

    IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/336

    CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L27/11568 ,  H01L29/66833

    Abstract: One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

Patent Agency Ranking