公开(公告)号：WO2004100230A2

公开(公告)日：2004-11-18

申请号：PCT/US2004/011354

申请日：2004-04-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED ,  FASTOW, Richard ,  HE, Yue-Song ,  MIZUTANI, Kazuhiro ,  THURGATE, Timothy

Inventor： FASTOW, Richard ,  HE, Yue-Song ,  MIZUTANI, Kazuhiro ,  THURGATE, Timothy

IPC: H01L21/00

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing (404) a dielectric material from an isolation region (110) situated in a substrate (258,358) to expose a trench (128,228), where the trench (128,228) is situated between a first source region (116,216,316) and a second source region (118,218), where the trench (128,228) defines sidewalls (150,250) in the substrate (258,358,). The method further comprises implanting (406) an N type dopant in the first source region (116,216,316), the second source region (118,218,318), and the sidewalls (150,250) of the trench (128,228), where the N type dopant forms an N+ type region (252,352). The method further comprises implanting (408) a P type dopant in the first source region (116,216,316), the second source region (118,218), and the sidewalls (150,250) of the trench (128,228), where the P type dopant forms a P type region (256,356), and where the P type region (256,356) is situated underneath the N+ type region (252,352).

Abstract translation: 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底（258,358）中的隔离区（110）去除（404）电介质材料以暴露沟槽（128,228）的步骤，其中 沟槽（128,228）位于第一源极区域（116,216,316）和第二源极区域（118,218）之间，其中沟槽（128,228）限定衬底（258,358）中的侧壁（150,250）。 该方法还包括在第一源区（116,216,316），第二源区（118,218,318）和沟槽（128,228）的侧壁（150,250）中注入（406）N型掺杂剂，其中N型掺杂剂形成N + 类型区域（252,352）。 该方法还包括在第一源区（116,216,316），第二源区（118,218）和沟槽（128,228）的侧壁（150,250）中注入（408）P型掺杂剂，其中P型掺杂剂形成P 类型区域（256,356），并且其中P型区域（256,356）位于N +型区域（252,352）下方。

公开(公告)号：WO2002095762A3

公开(公告)日：2002-11-28

申请号：PCT/US2002/004779

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WANG, Zhigang ,  FASTOW, Richard ,  HADDAD, Sameer ,  PARK, Sheung-Hee ,  CHANG, Chi

IPC: G11C16/10

Abstract: A source resistor or a positive voltage is couples to the source and a negative bias voltage is applied at the substance or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. In a system and method for performing an APDE (Automatic Program Disturb after Erase) process, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A bit line APDE (Automatic program Disturb after Erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A control gate APDE (Automatic Program Disturb after Erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. Alternatively, the source is coupled to the control gate for each flash memory cell in a self-biasing configuration such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.

公开(公告)号：WO2005038810A1

公开(公告)日：2005-04-28

申请号：PCT/US2004/030415

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

Abstract translation: 存储单元阵列（50）包括制造在半导体衬底（54）上的存储单元（52）的二维阵列。 存储单元（52）被布置成限定行方向（67）和限定列方向（69）的多列的多行。 每列存储单元（52）包括多个交替沟道区（58）和源/漏区（64）。 导电互连（72）位于每个源/漏区（64）上方并且仅耦合到另一个源极/漏极区（64）。 另一个源极/漏极区域（64）位于与该列相邻的第二列中。 导电互连（64）被定位成使得每隔一个导电互连（64）连接到列的右侧的相邻列，并且每隔一个导电互连连接到列的左侧的相邻列。 多个源极/漏极控制线（70）在相邻列的存储器单元（52）之间延伸并且电耦合到在相邻列之间耦合的每个导电互连（72）。

公开(公告)号：EP1395992A2

公开(公告)日：2004-03-10

申请号：EP02713624.1

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WANG, Zhigang ,  FASTOW, Richard ,  HADDAD, Sameer ,  PARK, Sheung-Hee ,  CHANG, Chi

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

Abstract: A source resistor or a positive voltage is couples to the source and a negative bias voltage is applied at the substance or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. In a system and method for performing an APDE (Automatic Program Disturb after Erase) process, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A bit line APDE (Automatic program Disturb after Erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A control gate APDE (Automatic Program Disturb after Erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. Alternatively, the source is coupled to the control gate for each flash memory cell in a self-biasing configuration such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.

公开(公告)号：EP1673781B1

公开(公告)日：2007-07-25

申请号：EP04784309.9

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

公开(公告)号：EP1673781A1

公开(公告)日：2006-06-28

申请号：EP04784309.9

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.