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公开(公告)号：DE60210387T2
公开(公告)日：2007-01-04
申请号：DE60210387
申请日：2002-09-11
Applicant: ALTERA CORP
Inventor： ANDRASIC STJEPAN WILLIAM , PATEL RAKESH H , LEE CHONG H
Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator ("VCO") includes a plurality of such delay cells connected in a closed loop series. Phase locked loop ("PLL") circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.
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公开(公告)号：DE60210387D1
公开(公告)日：2006-05-18
申请号：DE60210387
申请日：2002-09-11
Applicant: ALTERA CORP
Inventor： ANDRASIC STJEPAN WILLIAM , PATEL RAKESH H , LEE CHONG H
Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator ("VCO") includes a plurality of such delay cells connected in a closed loop series. Phase locked loop ("PLL") circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.
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公开(公告)号：JP2003179470A
公开(公告)日：2003-06-27
申请号：JP2002272354
申请日：2002-09-18
Applicant: ALTERA CORP
Inventor： ANDRASIC STJEPAN WILLIAM , PATEL RAKESH H , LEE CHONG H
Abstract: PROBLEM TO BE SOLVED: To provide a delay cell for a voltage-controlled oscillator (VCO), which is capable of realizing a wide operational band width, without being restricted by the power supply. SOLUTION: The delay cell has a selectable number of parallel connection load resistance transistors which can operate in parallel and the selectable number of bias current transistors which can operate in parallel. The VCO contains a plurality of delay cells of this type in a series closed loop. A phase- locked loop (PLL) circuit includes the VCO of this type, controlled by a phase/ frequency detecting circuit. By the capability of controlling the number of these transistors which are activated or non-activated in each of the delay cells, the PLL can have a very wide operational frequency range. Activation or non- activation can be controlled by a program or by another method. COPYRIGHT: (C)2003,JPO
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