公开(公告)号：WO2010045081A3

公开(公告)日：2010-07-22

申请号：PCT/US2009059874

申请日：2009-10-07

Applicant: ALTERA CORP ,  VIJAYARAGHAVAN DIVYA ,  WORTMAN CURT ,  LEE CHONG H

Inventor： VIJAYARAGHAVAN DIVYA ,  WORTMAN CURT ,  LEE CHONG H

IPC: H04B1/40

CPC classification number: H04B1/005 ,  G06F13/385 ,  H04L69/12 ,  H04L69/18

Abstract: Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer ("PCS") circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer ("PMA") circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent ("PMD") sub-layer circuitry.

Abstract translation: 本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。 可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。 所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路 从属（“PMD”）子层电路。

公开(公告)号：WO2010126679A3

公开(公告)日：2011-01-13

申请号：PCT/US2010029860

申请日：2010-04-02

Applicant: ALTERA CORP ,  WORTMAN CURT ,  LEE CHONG H ,  CLIFF RICHARD G

Inventor： WORTMAN CURT ,  LEE CHONG H ,  CLIFF RICHARD G

IPC: G11C7/00 ,  G06F15/76 ,  G11C5/02

CPC classification number: G06F17/5045 ,  G06F2217/84 ,  H03K19/17724 ,  H03K19/17732

Abstract: An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 4OG /10OG Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.

Abstract translation: 提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。 第二区包括标准逻辑单元和基本单元。 在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。 基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。 在一个实施例中，第二区域可以嵌入第一区域。 在另一个实施例中，第二区域围绕第一区域的周边限定。 可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。 在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用4OG / 10OG以太网替换用于基于计算的应用的诸如PCI Express的原始功能，例如PCI Express， 因特拉肯，用于有线应用。 还提供了一种设计集成电路的方法。

公开(公告)号：WO2007075962A3

公开(公告)日：2007-08-23

申请号：PCT/US2006048926

申请日：2006-12-20

Applicant: ALTERA CORP ,  VENKATA RAMANAND ,  PATEL RAKESH H ,  LEE CHONG H

Inventor： PATEL RAKESH H ,  LEE CHONG H

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17744 ,  H03K19/17784

Abstract: In a programmable logic device, some or all of the parallel interconnect resources (24) are replaced by serial interconnect resources (25) within the device. Some or all of the functional blocks (21, 22, 23) on the device are supplemented with serial interfaces (30) . Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces (30) may operate synchronously from a global device clock (such as a PLL) . In some cases, serial interfaces (30) that are provided in the input/output blocks (23) for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks (23) would have to be more complex because they would have to be able to operate asynchronously with external devices .

Abstract translation: 在可编程逻辑器件中，部分或全部并行互连资源（24）由器件内的串行互连资源（25）代替。 设备上的部分或全部功能块（21,22,23）被补充有串行接口（30）。 尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。 这意味着设备功耗的显着降低。 串行接口（30）可以从全局设备时钟（例如PLL）同步地操作。 在一些情况下，由于功能块中的串行接口可以接管外部串行接口功能，所以可以省略在用于外部信号的输入/输出块（23）中提供的串行接口（30），尽管在这些情况下 功能块（23）中的串行接口必须更复杂，因为它们必须能够与外部设备异步操作。

公开(公告)号：DE60215573T2

公开(公告)日：2007-06-21

申请号：DE60215573

申请日：2002-03-15

Applicant: ALTERA CORP A DELAWARE CORP

Inventor： LEE CHONG H ,  ASAYESH REZA

IPC: H03K19/173 ,  H03K19/177 ,  G06F15/78

Abstract: A programmable logic device ("PLD") includes high speed serial interface ("HSSI") circuitry that can support several high speed serial ("HSS") standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

公开(公告)号：AT456882T

公开(公告)日：2010-02-15

申请号：AT06005634

申请日：2006-03-20

Applicant: ALTERA CORP

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  PATEL RAKESH H

IPC: H03K19/177

Abstract: A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

公开(公告)号：DE60215573D1

公开(公告)日：2006-12-07

申请号：DE60215573

申请日：2002-03-15

Applicant: ALTERA CORP A DELAWARE CORP

Inventor： LEE CHONG H ,  ASAYESH REZA

IPC: H03K19/173 ,  H03K19/177 ,  G06F15/78

Abstract: A programmable logic device ("PLD") includes high speed serial interface ("HSSI") circuitry that can support several high speed serial ("HSS") standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

公开(公告)号：JP2007018498A

公开(公告)日：2007-01-25

申请号：JP2006086647

申请日：2006-03-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： VENKATA RAMANAND ,  PATEL RAKESH H ,  LEE CHONG H

IPC: G06F13/38 ,  G06F3/00 ,  H04L13/08 ,  H04L29/08

CPC classification number: H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide a serial interface capable of responding suitably to a wide range data rate. SOLUTION: A serial interface for a PLD (20) supports a wide range of the data rate by providing the first number of channels (21-24) for supporting the data rate of the first range and the second number of channels (200) for supporting the second range of the data rate. The data rate for the first range is lower than the data rate for the second range. The first number of the channels is larger than the number of the second channels which is preferably one. The number of the first channels in each of the interfaces is suitably four. Each of the channels includes a physical medium connection module (26) and a physically coded sublayer module (25). Each of the high-speed channels for the channels of the second number includes a clock management unit. The low-speed channel of the channel of the first number shares one or more clock management units. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供能够适应于宽范围数据速率的串行接口。 解决方案：PLD（20）的串行接口通过提供第一数量的通道（21-24）来支持宽范围的数据速率，用于支持第一范围和第二数量通道的数据速率 200）用于支持数据速率的第二范围。 第一范围的数据速率低于第二范围的数据速率。 通道的第一数量大于最好是一个的第二通道的数量。 每个接口中的第一个通道的数量适当地为4个。 每个通道包括物理介质连接模块（26）和物理编码子层模块（25）。 用于第二号码的频道的每个高速频道包括时钟管理单元。 第一个频道的低速频道共享一个或多个时钟管理单元。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006302277A

公开(公告)日：2006-11-02

申请号：JP2006107956

申请日：2006-04-10

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  PATEL RAKESH H

IPC: G06F13/38 ,  H03K19/173

CPC classification number: H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide a high-speed serial interface offering a wide-range data rate.
SOLUTION: This serial interface for the programmable logic device can work according to various communication protocols and includes a receiver part (350) and a transmitter part (370). The receiver part is provided with a word alignment step or a byte alignment step (321), a deskew step (322), a rate compensation step or a rate matching step (323), an embedded protocol decoder step (324), a byte serial-parallel converter step (325), a byte rearrangement step (326), and a phase compensation step (327) at least. The transmitter part includes a phase compensation step (371), a byte parallel/serial converter step (372), and an embedded protocol encoder step (373) at least. Each of the steps may have a plurality of associated circuits. A selection circuit (for example, a multiplexer) selects a proper step and a circuit in each step as to a protocol to be used.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供提供广泛数据速率的高速串行接口。 解决方案：用于可编程逻辑器件的该串行接口可以根据各种通信协议工作，并且包括接收器部分（350）和发射器部分（370）。 接收器部分设置有字对准步骤或字节对准步骤（321），偏移校正步骤（322），速率补偿步骤或速率匹配步骤（323），嵌入式协议解码器步骤（324），字节 串行并行转换器步骤（325），字节重排步骤（326）和相位补偿步骤（327）。 发射机部分至少包括相位补偿步骤（371），字节并行/串行转换器步骤（372）和嵌入式协议编码器步骤（373）。 每个步骤可以具有多个相关电路。 选择电路（例如，多路复用器）对于要使用的协议在每个步骤中选择适当的步骤和电路。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：DE602006011974D1

公开(公告)日：2010-03-18

申请号：DE602006011974

申请日：2006-03-20

Applicant: ALTERA CORP

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  PATEL RAKESH H

IPC: H03K19/177

Abstract: A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

公开(公告)号：DE602004009620D1

公开(公告)日：2007-12-06

申请号：DE602004009620

申请日：2004-01-20

Applicant: ALTERA CORP

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  LUI HENRY

IPC: H03L7/081 ,  G01R25/00 ,  H03L7/08 ,  H03L7/089 ,  H04L7/033

Abstract: Phase locked loop circuitry (150) operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals (154) the signal that is closest in phase to transitions in another signal (152) such as a clock data recovery ("CDR") signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal.