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    PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT
    1.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT 审中-公开
    具有串行互连的可编程逻辑器件

    公开(公告)号：WO2007075962A3

    公开(公告)日：2007-08-23

    申请号：PCT/US2006048926

    申请日：2006-12-20

    Applicant: ALTERA CORP ,  VENKATA RAMANAND ,  PATEL RAKESH H ,  LEE CHONG H

    Inventor： PATEL RAKESH H ,  LEE CHONG H

    IPC: H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/17744 ,  H03K19/17784

    Abstract: In a programmable logic device, some or all of the parallel interconnect resources (24) are replaced by serial interconnect resources (25) within the device. Some or all of the functional blocks (21, 22, 23) on the device are supplemented with serial interfaces (30) . Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces (30) may operate synchronously from a global device clock (such as a PLL) . In some cases, serial interfaces (30) that are provided in the input/output blocks (23) for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks (23) would have to be more complex because they would have to be able to operate asynchronously with external devices .

    Abstract translation: 在可编程逻辑器件中，部分或全部并行互连资源（24）由器件内的串行互连资源（25）代替。 设备上的部分或全部功能块（21,22,23）被补充有串行接口（30）。 尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。 这意味着设备功耗的显着降低。 串行接口（30）可以从全局设备时钟（例如PLL）同步地操作。 在一些情况下，由于功能块中的串行接口可以接管外部串行接口功能，所以可以省略在用于外部信号的输入/输出块（23）中提供的串行接口（30），尽管在这些情况下 功能块（23）中的串行接口必须更复杂，因为它们必须能够与外部设备异步操作。

    DIGITAL EQUALIZER FOR HIGH-SPEED SERIAL COMMUNICATIONS
    2.
    发明申请
    DIGITAL EQUALIZER FOR HIGH-SPEED SERIAL COMMUNICATIONS 审中-公开
    用于高速串行通信的数字均衡器

    公开(公告)号：WO2009137007A2

    公开(公告)日：2009-11-12

    申请号：PCT/US2009002652

    申请日：2009-04-29

    Applicant: ALTERA CORP ,  BEREZA WILLIAM W ,  VARELJIAN ALBERT ,  PATEL RAKESH H

    Inventor： BEREZA WILLIAM W ,  VARELJIAN ALBERT ,  PATEL RAKESH H

    IPC: H04B7/005 ,  H04B1/12 ,  H04B1/16

    CPC classification number: H04L25/0272

    Abstract: Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

    Abstract translation: 数字化高速串行接收机的传入数据，然后可以使用数字信号处理（DSP）技术来执行数字均衡。 这样的数字技术可以用于校正各种数据异常。 特别地，在可能涉及串扰的多通道系统中，其他通道的特性或甚至这些通道上的数据的知识可能允许减去串扰。 对数据通道几何的了解，特别是在背板传输的上下文中，可能允许减去连接器引起的回波和反射。 随着数据速率的提高，可以采用分数速率处理。 例如，可以以半速率执行模数转换，然后可以并行使用两个DSP，以在较高的初始时钟速率下维持吞吐量。 在更高的速率下，正交技术可以允许以四分之一速率进行模数转换，并行使用四个DSP。

    Multiple data rate in serial interface for programmable logic device
    3.
    发明专利
    Multiple data rate in serial interface for programmable logic device 有权
    用于可编程逻辑器件的串行接口中的多个数据速率

    公开(公告)号：JP2007018498A

    公开(公告)日：2007-01-25

    申请号：JP2006086647

    申请日：2006-03-27

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： VENKATA RAMANAND ,  PATEL RAKESH H ,  LEE CHONG H

    IPC: G06F13/38 ,  G06F3/00 ,  H04L13/08 ,  H04L29/08

    CPC classification number: H03K19/17744

    Abstract: PROBLEM TO BE SOLVED: To provide a serial interface capable of responding suitably to a wide range data rate. SOLUTION: A serial interface for a PLD (20) supports a wide range of the data rate by providing the first number of channels (21-24) for supporting the data rate of the first range and the second number of channels (200) for supporting the second range of the data rate. The data rate for the first range is lower than the data rate for the second range. The first number of the channels is larger than the number of the second channels which is preferably one. The number of the first channels in each of the interfaces is suitably four. Each of the channels includes a physical medium connection module (26) and a physically coded sublayer module (25). Each of the high-speed channels for the channels of the second number includes a clock management unit. The low-speed channel of the channel of the first number shares one or more clock management units. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够适应于宽范围数据速率的串行接口。 解决方案：PLD（20）的串行接口通过提供第一数量的通道（21-24）来支持宽范围的数据速率，用于支持第一范围和第二数量通道的数据速率 200）用于支持数据速率的第二范围。 第一范围的数据速率低于第二范围的数据速率。 通道的第一数量大于最好是一个的第二通道的数量。 每个接口中的第一个通道的数量适当地为4个。 每个通道包括物理介质连接模块（26）和物理编码子层模块（25）。 用于第二号码的频道的每个高速频道包括时钟管理单元。 第一个频道的低速频道共享一个或多个时钟管理单元。 版权所有（C）2007，JPO＆INPIT

    Programmable logic with embedded memory blocks
    4.
    发明专利
    Programmable logic with embedded memory blocks 未知

    公开(公告)号：GB2351824A

    公开(公告)日：2001-01-10

    申请号：GB0016223

    申请日：2000-06-30

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

    IPC: G11C5/02 ,  H03K19/177

    Abstract: A high-performance programmable logic architecture has embedded memory arranged at peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703,706) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements can be directly programmable routed and connected to driver blocks of the logic blocks in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources. Using similar direct programmable interconnections the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size

    A programmable interconnect junction
    6.
    发明专利
    A programmable interconnect junction 未知

    公开(公告)号：GB2312068A

    公开(公告)日：1997-10-15

    申请号：GB9707323

    申请日：1997-04-10

    Applicant: ALTERA CORP

    Inventor： PASS CHRISTOPHER J ,  SANSBURY JAMES D ,  MADURAWE RAMINDA U ,  TURNER JOHN E ,  PATEL RAKESH H ,  WRIGHT PETER J

    IPC: H03K19/177 ,  H03K19/0175

    Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line. An interconnect transistor 610 and a memory transistor 635 share a floating gate 620 which is charged via a write transistor 650 and tunnel diode 660 and controlled from a line 670 via a capacitor 680. A read transistor 630 can be used for margin testing.

    Programmable logic device with redundancy
    7.
    发明专利
    Programmable logic device with redundancy 未知

    公开(公告)号：GB2286914A

    公开(公告)日：1995-08-30

    申请号：GB9508878

    申请日：1995-01-31

    Applicant: ALTERA CORP

    Inventor： PATEL RAKESH H ,  WONG MYRON W

    IPC: G06F11/20 ,  H03K19/177

    Abstract: When a portion of a programmable logic device is found to be defective, redundant circuitry is switched into use in place of the defective circuitry. The programmable logic device is arranged in rows and columns of programmable logic containing logic array blocks 12, which a user selectively configures by loading programming data into vertical and horizontal programming blocks. When the redundant circuitry is switched into place, the programming data is redirected to the appropriate programing blocks. The outputs of each block 12 go to demultiplexers 24, multiplexers 28 and tristate drivers 26 connected to row and column conductors. When a defective row of blocks 12 is switched out of use, a spare row being switched in, input/output pins 18 for the row conductors are reconnected to respective adjacent rows instead, as necessary (by circuitry not shown in Fig. 2).

    DELAY CELL FOR VOLTAGE-CONTROLLED OSCILLATOR
    8.
    发明专利
    DELAY CELL FOR VOLTAGE-CONTROLLED OSCILLATOR 审中-公开

    公开(公告)号：JP2003179470A

    公开(公告)日：2003-06-27

    申请号：JP2002272354

    申请日：2002-09-18

    Applicant: ALTERA CORP

    Inventor： ANDRASIC STJEPAN WILLIAM ,  PATEL RAKESH H ,  LEE CHONG H

    IPC: H03H11/26 ,  H03K3/03 ,  H03K3/354 ,  H03K5/13 ,  H03L7/099 ,  H03L7/10

    Abstract: PROBLEM TO BE SOLVED: To provide a delay cell for a voltage-controlled oscillator (VCO), which is capable of realizing a wide operational band width, without being restricted by the power supply. SOLUTION: The delay cell has a selectable number of parallel connection load resistance transistors which can operate in parallel and the selectable number of bias current transistors which can operate in parallel. The VCO contains a plurality of delay cells of this type in a series closed loop. A phase- locked loop (PLL) circuit includes the VCO of this type, controlled by a phase/ frequency detecting circuit. By the capability of controlling the number of these transistors which are activated or non-activated in each of the delay cells, the PLL can have a very wide operational frequency range. Activation or non- activation can be controlled by a program or by another method. COPYRIGHT: (C)2003,JPO

    Embedded memory blocks for programmable logic
    9.
    发明专利
    Embedded memory blocks for programmable logic 未知

    公开(公告)号：GB2391671A

    公开(公告)日：2004-02-11

    申请号：GB0324461

    申请日：2000-06-30

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

    IPC: H03K19/177

    Abstract: A high-performance programmable logic architecture has embedded memory arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703,706) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements can be directly programmable routed and connected to driver blocks of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources. Using similar direct programmable interconnections the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources.

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